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Data Sheet
C-3e NETWORK PROCESSOR SILICON REVISION A1
C3ENPA1-DS/D Rev 03 PRELIMINARY
Data Sheet
C-3e Network Processor Silicon Revision A1
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C3ENPA1-DS/D Rev 03
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Copyright (c) 2002 Motorola, Inc. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Motorola. Motorola reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Motorola to provide notification of such revision or change. Motorola provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. Motorola may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. C-5e, C-3e, C-5, Q-5, Q-3, C-Port, and C-Ware are all trademarks of C-Port, a Motorola Company. Motorola and the stylized Motorola logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
C3ENPA1-DS/D Rev 03
CONTENTS
About This Guide
Guide Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using PDF Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 14 16 16 17
CHAPTER 1
Functional Description
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Massive Processing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Functional Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 20 22 23 23 24 24 25 26
CHAPTER 2
Signal Descriptions
Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 30 30 31 31 34 35 36
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
6
CONTENTS
Gigabit Ethernet and Fibre Channel TBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SONET OC-3 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SONET OC-12 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU SRAM (Internal Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU to Q-5/Q-3 (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDcode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38 40 41 43 43 44 45 48 49 51 53 54 55 56 57 58 67 67 67 67 67 69 69 70
CHAPTER 3
Electrical Specifications
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Package Conduction Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heat Sink Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 72 73 74 75 75 76 77 79 80 81
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MOTOROLA GENERAL BUSINESS INFORMATION
CONTENTS
7
DS1/DS3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10/100 Ethernet Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications . . . . . . . . . . . . . . . . . . 83 OC-3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 OC-12 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Executive Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 MDIO Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Low Speed Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PROM Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Fabric Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 BMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 TLU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 QMU SRAM (Internal Mode) Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 QMU to Q-5/Q-3 (External Mode) Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
CHAPTER 4
Mechanical Specifications
Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 106 106 107
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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CONTENTS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D Rev 03
LIST OF FIGURES
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
C-3e Network Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Locations (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Cell Design That Can Be Used for Both Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . 68 Bringup Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Package Cross Section View with Serveral Heat Sink Options . . . . . . . . . . . . . . . . . . . . . . . 76 Package with Heat Sink Mounted to the Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . 77 Test Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 QMU SRAM (Internal Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 QMU to Q-5/Q-3 (External Mode) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 C-3e Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 C-3e Network Processor BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 C-3e Network Processor BGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
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LIST OF FIGURES
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D Rev 03
LIST OF TABLES
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Navigating Within a PDF Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C-3e Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C-Port Silicon Documentation Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TLU SRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . . . . . . 36 Gigabit Ethernet (GMII/MII) Signals One Cluster Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PROM Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Fabric Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Utopia1*, 2, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping . . . . . . 50 Utopia1*, 2, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping . . . . . . . 50 BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 QMU SRAM (Internal Mode) Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 QMU to Q-5/Q-3 (External Mode) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Power Supply Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . . . . 57 Signals Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 JTAG Internal Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 C-3e Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 C-3e Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .72 C-3e Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C-3e Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C-3e Network Processor Power and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 QMU SRAM (Internal Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .99 QMU to Q-5/Q-3 (External Mode) Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Signal Groups in QMU to Q-5/Q-3 (External Mode) Timimg Diagrams . . . . . . . . . . . . . . . . . . . 101 Package Measurements (Reference Figure 28, Figure 29 and Figure 30 for Symbols). . . . 106 C-3e Network Processor Marking Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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Guide Overview
The C-3e Network Processor Data Sheet describes the hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. This document contains information on a pre-production product. Specifications and information herein are subject to change without notice. This guide assumes a good understanding of the C-3eTM Network Processor (NP) architecture. See the C-5e/C3e Network Processor Architecture GuidE (part number C5EC3EARCH-RM/D) for more detail about how the hardware works. This guide also assumes good working knowledge of the C-Ware Software Toolset. This guide covers the following topics:
* * * *
Functional Description Signal Descriptions Electrical Specifications Mechanical Specifications
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Data Sheet Classifications
Table 1 describes the Data Sheet classifications of Advance, Preliminary, and Production.
Table 1 Data Sheet Classifications
CLASSIFICATION DESCRIPTION
Advance Information
Used to advise customers of the proposed addition to the product line. This document will typically contain some useful information including interfacing with the user's system and some specifications. The goal of this document is to allow customers to begin designs but with expectation of changes. Specification details may be changed later without notice. Describes pre-production or first production devices and is usually indicative of production stage performance. Minor changes should be expected as characteristic spreads become better controlled. Specification details may be changed slightly without notice, but the customer can design their product based on this data sheet. Defines the long-term specified production limits based on fully characterized data. It includes a disclaimer to allow improvements in specifications and modifications that do not affect form, fit or function in original applications; if absolute maximum ratings are changed, they should improve rather than downgrade.
Preliminary Information
Production Data
Using PDF Documents
Electronic documents are provided as PDF files. Open and view them using the Adobe(R) Acrobat(R) Reader application, version 3.0 or later. If necessary, download the Acrobat Reader from the Adobe Systems, Inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html PDF files offer several ways for moving among the document's pages, as follows:
*
To move quickly from section to section within the document, use the Acrobat bookmarks that appear on the left side of the Acrobat Reader window. The bookmarks provide an expandable outline view of the document's contents. To display the document's Acrobat bookmarks, press the "Display both bookmarks and page" button on the Acrobat Reader tool bar. To move to the referenced page of an entry in the document's Contents or Index, click on the entry itself, each of which is hyperlinked. To follow a cross-reference to a heading, figure, or table, click the blue text.
* *
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Using PDF Documents
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*
To move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the Acrobat Reader navigation buttons shown in this figure:
Beginning of document End of Previous or next hyperlink Previous Next page
Table 2 summarizes how to navigate within an electronic document.
Table 2 Navigating Within a PDF Document
TO NAVIGATE THIS WAY CLICK THIS
Move from section to section within the document. Move to an entry in the Table of Contents. Move to an entry in the Index. Move to an entry in the List of Figures or List of Tables.
A bookmark on the left side of the Acrobat Reader window The entry itself The page number The Figure or Table number
Follow a cross-reference (highlighted in blue The cross-reference text text). Move page by page. Move to the beginning or end of the document. The appropriate Acrobat Reader navigation buttons The appropriate Acrobat Reader navigation buttons
Move backward or forward among a series of The appropriate Acrobat Reader navigation hyperlinks you have selected. buttons
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Guide Conventions
The following visual elements are used throughout this guide, where applicable: This icon and text designates information of special note.
Warning: This icon and text indicate a potentially dangerous procedure. Instructions contained in the warnings must be followed.
Warning: This icon and text indicate a procedure where the reader must take precautions regarding laser light.
This icon and text indicate the possibility of electrostatic discharge (ESD) in a procedure that requires the reader to take the proper ESD precautions.
Revision History
Table 3 provides details about changes made for each revision of this guide.
Table 3 C-3e Network Processor Data Sheet Revision History
REVISION DATE CST REVISION CDS REVISION CHANGES
November 8, 2002
2.2
2.0
* Added information about optional
capacitors, nominal values for recommended operating conditions, and updated package measurement values. * Pin number typographical correction in Table 28, pin AF12 corrected to FIN4 (instead of FIN14), and pin AE5 corrected to PAD23 (instead of PAD27). * Typographic corrections throughout.
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Related Product Documentation
Table 4 lists the user and reference documentation for Motorola `s C-Port silicon documentation set.
Table 4 C-Port Silicon Documentation Set
DOCUMENT SUBJECT DOCUMENT NAME PURPOSE DOCUMENT ID
Processor C-5 Network Processor Architecture Guide Information C-5 Network Processor Data Sheet C-5e/C-3e Network Processor Architecture Guide C-5e Network Processor Data Sheet C-3e Network Processor Data Sheet C-5 Network Processor to C-5e Network Processor Comparison Delta Document M-5 Channel Adapter Architecture Guide M-5 Channel Adapter Data Sheet Q-5/Q-3 Traffic Management Coprocessor Architecture Guide Q-5 Traffic Management Coprocessor Data Sheet
Describes the full architecture of the C-5 network processor. Describes hardware design specifications for the C-5 network processor.
C5NPARCH-RM/D C5NPDATA-DS/D
Describes the full architecture of the C-5e and C-3e C5EC3EARCH-RM/D network processors. Describes hardware design specifications for the C-5e network processor. Describes hardware design specifications for the C-3e network processor. Describes key architectural features of the C-5e, and highlights main differences between C-5 and C-5e. Describes the full architecture of the M-5 channel adapter. Describes hardware design specifications for the M-5 channel adapter. Describes the full architecture of the Q-5 and Q-3 traffic management coprocessor. Describes hardware design specifications for the Q-5 traffic management coprocessor. C5ENPA1-DS/D C3ENPA1-DS/D C5C5EDELTA-RM/D
M5CAARCH-RM/D M5CA0-DS/D Q5Q3ARCH-RM/D Q5TMCA0-DS/D
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FUNCTIONAL DESCRIPTION
Features
Key features of the C-3eTM Network Processor (NP) are its massive processing capabilities and its high level of functional integration on one chip.
Massive Processing Power
* * * * * * * *
Operating frequencies: up to 180MHz 3Gbps of bandwidth (for non-blocking throughput) More than 3,000MIPS of computing power (for adding services throughout the protocol stack) Up to 9 million packets per second transmitted at wire speed 17 programmable RISC Cores (for cell/packet forwarding) 32 programmable Serial Data Processors (for processing bit streams) Up to 133 million table lookups per second Three internal buses for 46Gbs of aggregate bandwidth 728 pin Ball Grid Array (BGA) package 16 Channel Processors (8 CP's with full functionality configurable for full I/O or recirculation, and 8 CP's with limited functionality configurable only for bit and byte level recirculation) including: - Embedded OC-3c, OC-12, OC-12c SONET framers - Programmable MAC interface - RISC Cores - Programmable pin PHY interfaces
High Functional Integration
* *
*
Embedded coprocessors for table lookup (classification), buffer management (payload control), and queue management (QoS implementation)
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* * *
Block Diagram
Dedicated Fabric Processor and port Embedded RISC Executive Processor Integrated 32bit 33/66MHz PCI bus interface
The C-3eTM NP, has an architecture specifically designed for networking applications. The following sections describe each component of the C-3e NP. The main components of the C-3e NP are:
* * * * * *
Channel Processors Executive Processor Fabric Processor Buffer Management Unit Table Lookup Unit Queue Management Unit
The C-3e NP conforms with both SONET and SDH. Therefore, OC-3(STS-3/STM-1), and OC-12 (STS-12/STM-4). Figure 1 shows a block diagram of the C-3e NP, including its potential external interfaces. For more information about the architecture of the C-3e NP, see the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D).
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Block Diagram
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Figure 1 C-3e Network Processor Block Diagram
Q-5 or Q-3 (optional) SRAM Fabric SRAM External Host CPU (optional) External PROM (optional) SDRAM
Control Logic (optional) Table Lookup Unit
PCI Serial PROM
Fabric Processor
Executive Processor Buffer Mgmt Unit
Queue Mgmt Unit
Buses (64Gbps Bandwidth)
C-3e NP
CP-0 CP-1 CP-2 CP-3
Cluster PHY PHY PHY PHY
CP-12 CP-13 CP-14 CP-15
Cluster
Channel Processors
Processor Boundary 16 Channel Processors: 8 (CP0 to CP7) full functionality 8 (CP8 to CP15) Internal-only
PHY Interface Examples: 10/100 Ethernet Gigabit Ethernet - Aggregated OC-3 OC-12
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Channel Processors
The C-3e NP contains eight programmable external Channel Processors (CPs) that receive, process, and transmit network data, plus an additional eight internal CPs that process data. Typically one CP is assigned to each port for medium bandwidth applications (Fast Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an external multiplexor, for low bandwidth applications, such as DS1 to DS3. The C-3e NP's architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including:
* * * * * *
10/100Mb Ethernet (RMII) 1Gb Ethernet (GMII and TBI) OC-3c OC-12 100Mbit FibreChannel DS1/DS3, supported through the use of external framers/multiplexors
The C-3e NP's programmability can also support a variety of special interfaces, such as various xDSL encapsulations and proprietary protocols. Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called Serial Data Processors (SDPs), that provide features such as Ethernet MAC and SONET/SDH framing, multichannel HDLC, and ATM cell delineation. This means you usually only need to include PHYs to complete the system.
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Executive Processor
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Executive Processor
The Executive Processor (XP) serves as a centralized computing resource for the C-3e NP and manages the system interfaces. The XP performs conventional supervisory tasks in the C-3e NP, including:
* * * * *
System Interfaces
Reset and initialization of the C-3e NP Program loading and control of CPs Centralized exception handling Management of a host interface through the PCI Management of system interfaces (PCI, Serial Bus, PROM)
The system interfaces to the XP are:
* *
PCI -- Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level shared resources. The PCI has both initiator and target capabilities. The PCI interface is typically connected to a host processor. Serial Bus Interface -- Provides a general purpose bi-directional, two-wire serial bus and I/O port that allows the C-3e NP to control external logic with either of two standard protocols: - The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of addressing and supports transfers up to 25MHz. - The low-speed protocol: uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. Software is used to select which protocol to use, by setting the appropriate bits in the Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is driven by the C-3e NP to indicate which protocol is being used (SPLD=0 indicates MDIO protocol; SPLD=1 indicates low-speed protocol). Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because of the pull-up resistor. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
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*
PROM Interface -- Allows the XP to boot from nonvolatile, flash memory. The PROM interface is a low-speed, serial I/O port that runs at 1/2 to 1/16 the core clock rate. The maximum PROM size addressable is 4MBytes, and must use a "by 16" part. External board logic is required to perform serial-to-parallel conversion for PROM address outputs and parallel-to-serial conversion for PROM data inputs.
Fabric Processor
The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C-3e NP to interface to an application-specific switching solution internal to your design. The FP port supports the bidirectional transfer of segments from the C-3e NP to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. There are numerous parameters that can be configured within the FP to allow the interface to be adapted to different fabric protocols. The FP can be configured to conform to three (3) different fabric interfaces that include: UTOPIA-1, -2, -3. The FP can be configured to run at any frequency up to 125MHz, with the receive and transmit data buses up to 16 bits wide. This allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 2000 Mbps full duplex bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-3e NP to external pipeline architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It is also used as second level storage in the XP memory hierarchy. The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine SECDED (single error correction-double error detection) ECC (error correction code) bits. The interface is compliant with the PC100 standard and operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D) for more details). The C-3e NP non-configurable interface transfers four beats of data for each read and write using a sequential burst type. In addition, the C-3e NP uses an auto-refresh mode for the RAM's.
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Table Lookup Unit
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Some of these parameters are programmed into the SDRAMs' mode register and can be applied only once per power cycle. The ECC functionality can be enabled or disabled via configuration register writes. If needed, the interface can narrowed to 128bits by disabling ECC and providing board pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU supports SDRAM devices that use 12 address lines. Internal address calculation paths limit the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
Table Lookup Unit
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used for statistics accumulation and retrieval and as general data storage. The TLU simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and QoS lookup tasks. The C-3e NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules (at frequencies up to 125MHz) for storage of its tables. These modules allow implementation of tables with 225 x 64bit entries using 8Mbit SRAM technology. The maximum amount of memory supported by the TLU is 128MBytes in four banks, when SRAM technology supports 4M x 18pins parts.
Table 5 TLU SRAM Configurations
SRAM TECHNOLOGY MIN TABLE SIZE (ONE BANK) MAXIMUM TABLE SIZE (FOUR BANKS)
1Mbit (32k x 32pins) 2Mbit (64k x 32pins) 4Mbit (256k x 18pins) 8Mbit (512k x 18pins) 16Mbit (1M x 18pins) 32Mbit (2M x 18pins) 64Mbit (4M x 18pins)
256kBytes 512kBytes 2MBytes 4MBytes 8MBytes 16MBytes 32MBytes
1MBytes 2MBytes 8MBytes 16MBytes 32MBytes 64MBytes 128MBytes
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Queue Management Unit
The Queue Management Unit (QMU) autonomously manages a number of application-defined descriptor queues. It handles inter-CP and inter-C-3e NP descriptor flows by providing switching and buffering. It also performs descriptor replication for multicast applications. A number of up to 128 queues can be assigned to each CPRC for QoS-based services. The QMU provides a queuing engine internal to the chip and uses external SRAM to store the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and 16, 384 descriptor buffers. A descriptor buffer holds an application-defined "descriptor" , which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. The QMU's external SRAM interface uses ZBT synchronous SRAMs organized in a single bank of up to 128k, 32bit words. This interface runs at up to 150MHz frequency. The C-3e provides two modes for managing queues. They consist of:
* *
Internal Mode (using the internal QMU only) External Mode (using the internal QMU and the external Q-5 Traffic Management Coprocessor, or using the internal QMU and the external Q-3 Traffic Management Coprocessor).
See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D), as well as, the Q-5/Q-3 Traffic Management Coprocessor Architecture Guide (part number Q5Q3ARCH-RM/D) for more details.
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SIGNAL DESCRIPTIONS
Signal Summary
There are nine (9) functional groupings of signals in the C-3e Network Processor:
* * *
Clock -- 7 pins Channel Processors (CP0 - CP7) -- 8x7 = 56 pins Executive Processor (XP) -- 57 pins - PCI Interface -- 50 pins - PROM Interface -- 4 pins - Serial Bus Interface -- 2 pins - General System Interface -- 1 pin
* * * * * *
Fabric Processor (FP) -- 42 pins Buffer Management Unit (BMU) -- 160 pins Table Lookup Unit (TLU) -- 99 pins Queue Management Unit (QMU) -- 59 pins Power -- 234 pins Test -- 14 pins
Two (2) of the sections (CPs and FP) are configurable, depending on the type of device being implemented.
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Pinout Diagram
The C-3e NP contains 728 pins. These pin numbers are referenced throughout the remaining chapter. Figure 2 shows the pin locations from the top view. In contrast, Figure 3 shows the pin locations from the bottom view.
Figure 2 Pin Locations (Top View)
27 AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 MD0 MD6 MD13 MD20 MD26 MD34 MD41 MD49 MD55 MD63 MD70 MD78 MD84 MD91 MD98 MD104 MD112 MD119 MD125 MDECC6 26 CP0_6 VDD33 CP1_0 GND CP1_1 CP1_2 VDD33 MD7 MD14 GND MD27 MD35 MD42 VDD33 MD56 MD64 MD71 GND MD85 MD92 VDD33 MD105 MD113 GND MD126 25 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 MD1 MD8 MD15 MD21 MD28 MD36 MD43 MD50 MD57 MD65 MD72 MD79 MD86 MD93 MD99 MD106 MD114 MD120 MD127 24 CP2_2 CP2_3 VDD33 CP2_4 GND CP2_5 MD2 GND VDD33 MD22 MD29 GND MD44 MD51 MD58 VDD33 MD73 MD80 GND VDD33 MD100 MD107 GND MD121 VDD33 23 CP2_6 CP3_0 CP3_1 CP3_2 CP3_3 CP3_4 MD3 MD9 MD16 MD23 MD30 MD37 MD45 MD52 MD59 MD66 MD74 MD81 MD87 MD94 MD101 MD108 MD115 MD122 MD128 22 CP3_5 GND CP3_6 VDD33 CP4_0 CP4_1 GND MD10 MD17 VDD33 MD31 MD38 MD46 GND MD60 MD67 MD75 VDD33 MD88 MD95 GND MD109 MD116 VDD33 21 CP4_2 CP4_3 CP4_4 CP4_5 CP4_6 CP5_0 MD4 MD11 MD18 MD24 MD32 MD39 MD47 MD53 MD61 MD68 MD76 MD82 MD89 MD96 MD102 MD110 MD117 MD123 20 CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 MD5 MD12 MD19 MD25 MD33 MD40 MD48 MD54 MD62 MD69 MD77 MD83 MD90 MD97 MD103 MD111 MD118 MD124 19 CP6_0 18 17 16 FOUT2 FOUT3 15 FOUT8 FOUT9 14 13 12 11 FIN9 10 FIN15 VDD33 9 FRXCLK PAD3 PAD2 GND PAD1 PAD0 VDD33 GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT QACLKO QACLKI GND QDPL QDPH QNQRDY 9 8 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 7 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 6 PAD19 GND PAD18 VDD33 PAD17 PAD16 GND SPDI TA17 VDDT TA4 TCE0X 5 4 3 2 1 AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 CP6_5 FOUT0 FOUT14 FTXCTL2 FIN3 GND PAD25 PAD29 PCBEX1 PDEVSELX PPAR PAD24 PAD28 PCBEX2 PAD23 VDD33 PCBEX3 PAD22 PAD27 PSERRX PAD21 GND PPERRX PAD31 PAD30 XPUHOT TA15 TA8 TA1 TPAR2 TD63 TD56 TD49 TD42 TD34 TD27 TD21 TD14 TD7 TD0 QD9 QD10 QD11 QD12 QD13 3 VDD33 PSTOPX GND PIRDYX PCLK PRSTX PREQX PINTA
CP6_1 VDD33 FOUT1 CP6_2 GND CP6_3 CP6_4 VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 MBA0 MBA1 GND MA0 MA1 MA2 19 CP6_6 CP7_3 CP7_0 CP7_4 CP7_1 CP7_5 CP7_2 CP7_6 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 GND MA3 MA4 MA5 MA6 VDD33 MA7 18 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 MA8 MA9 MA10 MA11 JTCK JTMS 17
FTXCTL6 FIN4 FIN10
FOUT4 FOUT10 FOUT15 FTXCLK FIN5 FIN11 FRXCTL0 FOUT5 FOUT11 VDD33 FIN0 FIN1 FIN2 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 QA14 QA15 QA16 JSO0 JSO1 JSO2 13 FIN6 FIN12 FRXCTL1 FIN7 FIN13 FRXCTL2 FIN8 FIN14 FRXCTL6 GND VDD33 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND QARDY QWEX QA0 QA1 VDDT QA2 10
FOUT6 FOUT12 FTXCTL0 FOUT7 FOUT13 FTXCTL1 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND CCLK0 CCLK1 CPREF JTDI GND VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 SCLKX CCLK2 JSE JSO5 JHIGHZ GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 GND SCLK CCLK3 VDD33 JTDO JSO3 JSO4 14
PAD20 PAD26 PIDSEL SPDO TA16 TA10 TA3 TPAR3 SIDA GND VDDT TA9 TA2 GND
PCBEX0 PTRDYX VDDT TA21 TA14 GND TA0 TPAR1 TD62 VDDT TD48 TD41 TD33 GND TD20 TD13 VDDT QD5 QD6 GND QD7 VDDT QD8 2 SICL TA20 TA13 TA7 TCE3X TPAR0 TD61 TD55 TD47 TD40 TD32 TD26 TD19 TD12 TD6 QD0 QD1 QD2 QD3 QD4
PGNTX PFRAMEX SPCK TA19 TA12 TA6 TCE2X TWE3X TD60 TD54 TD46 TD39 TD31 TD25 TD18 TD11 TD5 QD30 QD31 QDQPAR QBCLKO QBCLKI 8 SPLD TA18 TA11 TA5 TCE1X TWE2X TD59 TD53 TD45 TD38 TD30 TD24 TD17 TD10 TD4 QD25 QD26 QD27 QD28 QD29 7
TWE1X TWE0X TCLKI GND TD52 TD44 TD37 VDDT TD23 TD16 GND TD3 QD22 VDDT QD23 GND QD24 6 TD58 TD51 TD43 TD36 TD29 TD22 TD15 TD9 TD2 QD17 QD18 QD19 QD20 QD21 5 TD57 TD50 VDDT TD35 TD28 GND VDDT TD8 TD1 GND QD14 VDDT QD15 QD16 4
GND VDDT QA9 QA10 QA11 QA12 GND QA13 12 QA3 QA4 QA5 QA6 QA7 QA8 11
MD129 MDECC8 MDECC7 GND MDECC2 MDECC1 MDQML 21 MDQM 20
VDD33 MDECC5 MDECC4 MDECC3 MCSX 25 MCASX 24
MDECC0 MDCLK 27 26
MRASX MWEX 23 22
JTRSTX JCLKBYP 16 15
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Figure 3 Pin Locations (Bottom View)
1 AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 8 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 9 FRXCLK PAD3 PAD2 GND PAD1 PAD0 VDD33 GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT GND VDDT 10 FIN15 VDD33 11 FIN9 FIN10 12 13 14 15 16 17 18 19 20 21 22 23 24 CP2_2 CP2_3 VDD33 CP2_4 GND CP2_5 MD2 GND VDD33 MD22 MD29 GND MD44 MD51 MD58 VDD33 MD73 MD80 GND VDD33 MD100 MD107 GND MD121 VDD33 25 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 MD1 MD8 MD15 MD21 MD28 MD36 MD43 MD50 MD57 MD65 MD72 MD79 MD86 MD93 MD99 26 CP0_6 VDD33 CP1_0 GND CP1_1 CP1_2 VDD33 MD7 MD14 GND MD27 MD35 MD42 VDD33 MD56 MD64 MD71 GND MD85 MD92 VDD33 27 CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 MD0 MD6 MD13 MD20 MD26 MD34 MD41 MD49 MD55 MD63 MD70 MD78 MD84 MD91 MD98 MD104 MD112 MD119 MD125 AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A PPAR PDEVSELX PCBEX1 PAD29 PAD25 PAD19 PCLK VDD33 PCBEX2 PAD28 PAD24 GND FIN3 FTXCTL2 FOUT14 FOUT8 FOUT2 FOUT0 CP6_5 CP6_0 CP5_1 FIN4 FTXCTL6 GND FOUT9 FOUT3 FOUT1 VDD33 CP6_1 CP5_2 CP4_2 CP3_5 CP2_6 CP4_3 GND CP3_0
PRSTX PSTOPX PREQX PINTA GND PIRDYX
PCBEX3 VDD33 PAD23 PAD18 PSERRX PAD27 PAD22 VDD33 PPERRX PAD31 PAD30 XPUHOT TA15 TA8 TA1 TPAR2 TD63 TD56 TD49 TD42 TD34 TD27 TD21 TD14 TD7 TD0 QD9 QD10 QD11 QD12 QD13 3 GND PAD21 PAD17
FRXCTL0 FIN11 FRXCTL1 FIN12 FRXCTL2 FIN13 FRXCTL6 FIN14 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND
FIN5 FTXCLK FOUT15 FOUT10 FOUT4 CP7_3 CP6_6 CP6_2 CP5_3 FIN6 FIN7 FIN8 FIN0 FIN1 FIN2 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 QA14 QA15 QA16 JSO0 JSO1 JSO2 13 VDD33 FOUT11 FOUT5 CP7_4 CP7_0 GND CP5_4
CP4_4 CP3_6 CP3_1 CP4_5 VDD33 CP3_2 CP4_6 CP4_0 CP3_3 CP5_0 CP4_1 CP3_4 MD4 MD11 MD18 MD24 MD32 MD39 MD47 MD53 MD61 MD68 MD76 MD82 MD89 MD96 MD102 GND MD10 MD17 VDD33 MD31 MD38 MD46 GND MD60 MD67 MD75 VDD33 MD88 MD95 GND MD3 MD9 MD16 MD23 MD30 MD37 MD45 MD52 MD59 MD66 MD74 MD81 MD87 MD94 MD101
FTXCTL0 FOUT12 FOUT6 CP7_5 CP7_1 CP6_3 CP5_5 FTXCTL1 FOUT13 FOUT7 CP7_6 CP7_2 CP6_4 CP5_6 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 GND SCLK CCLK3 VDD33 JTDO JSO3 VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 MA8 MA9 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD33 GND MA3 MA4 MA5 MA6 VDD33 MA7 18 VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND VDD33 GND MD5 MD12 MD19 MD25 MD33 MD40 MD48 MD54 MD62 MD69 MD77 MD83 MD90 MD97
PTRDYX PCBEX0 SICL TA20 TA13 TA7 TCE3X TPAR0 TD61 TD55 TD47 TD40 TD32 TD26 TD19 TD12 TD6 QD0 QD1 QD2 QD3 QD4 VDDT TA21 TA14 GND TA0 TPAR1 TD62 VDDT TD48 TD41 TD33 GND TD20 TD13 VDDT QD5 QD6 GND QD7 VDDT QD8 2
PAD26 PAD20 PAD16 SIDA GND VDDT TA9 TA2 GND PIDSEL SPDO TA16 TA10 TA3
GND PFRAMEX PGNTX SPDI TA17 VDDT TA4 SPLD TA18 TA11 TA5 SPCK TA19 TA12 TA6 TCE2X TWE3X TD60 TD54 TD46 TD39 TD31 TD25 TD18 TD11 TD5 QD30 QD31
VDD33 GND GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDDT QA3 QA4 QA5 QA6 QA7 QA8 11 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND QA9 QA10 QA11 QA12 GND QA13 12
TPAR3 TCE0X TCE1X
TCLKI TWE0X TWE1X TWE2X TD57 TD50 VDDT TD35 TD28 GND VDDT TD8 TD1 GND QD14 VDDT QD15 QD16 4 TD58 TD51 TD43 TD36 TD29 TD22 TD15 TD9 TD2 QD17 QD18 QD19 QD20 QD21 5 GND TD52 TD44 TD37 VDDT TD23 TD16 GND TD3 QD22 VDDT QD23 GND QD24 6 TD59 TD53 TD45 TD38 TD30 TD24 TD17 TD10 TD4 QD25 QD26 QD27 QD28 QD29 7
VDD33 MD103 MBA0 MBA1 GND MD111 MD118 MD124
QACLKO QARDY QACLKI GND QWEX QA0 QA1 VDDT QA2 10
SCLKX CCLK0 CCLK2 CCLK1 JSE JSO5 JHIGHZ
MD110 MD109 MD108 MD117 MD116 MD115 MD123 VDD33 MD122
MD106 MD105 MD114 MD113 MD120 GND
CPREF MA10 JTDI GND MA11 JTCK
QDQPAR QDPL QBCLKO QDPH QBCLKI QNQRDY 8 9
MA0 MDECC7 MDECC8 MD129 MD128
MD127 MD126
MA1 MDECC1 MDECC2 GND MDECC3 MDECC4 MDECC5 VDD33 MDECC6 MA2 19 MDQM 20 MDQML MWEX MRASX MCASX 21 22 23 24 MCSX MDCLK MDECC0 25 26 27
JSO4 JCLKBYPJTRSTX JTMS 14 15 16 17
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Pin Descriptions Grouped by Function
The C-3e NP pins are categorized in groups, reflecting interfaces to the chip:
* * * * * * * * * *
Clock Signals CP Interface Signals Executive Processor System Interface Signals Fabric Processor Interface Signals BMU SDRAM Interface Signals TLU SRAM Interface Signals QMU SRAM (Internal Mode) Interface Signals QMU to Q-5/Q-3 (External Mode) Interface Signals Power Supply Signals Test Signals
Pins conform to Joint Electronic Devices Engineering Council (JEDEC) standards.
LVTTL and LVPECL Specifications
C-3e NP pins are the following types:
* *
Low Voltage TTL-Compatible (LVTTL). The C-3e NP's LVTTL pins conform to the JEDEC JESD8-B specification. Low Voltage Positive Emitter Coupled Logic (LVPECL).
All of the signals in the following tables in this chapter denote whether the individual signal is an Input (I), Output (O), both Input and Output (I/O), or power (P). In addition, a PU, PD, and nc are used. The PU indicates that an internal resistor will pullup the pad if left unconnected. PD indicates an internal pulldown resistor. NC means the pad is to be left unconnected.
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Clock Signals
Table 6 describes the C-3e NP clock signals.
Table 6 Clock and Reference Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
SCLK* SCLKX* CCLK0 CCLK1 CCLK2 CCLK3 CPREF
TOTAL
*
F14 F15 F16 E16 E15 E14 D16
1 1 1 1 1 1 1
7
LVPECL LVPECL LVTTL LVTTL LVTTL LVTTL LVPECL
I I IPD IPD IPD IPD IPD
Core Clock Rate (Differential) Programmable CP Clock Input Programmable CP Clock Input Programmable CP Clock Input Programmable CP Clock Input Reference
SCLK and SCLKX must not be AC-coupled. If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must be wired to an external reference, as specified in Table 34 on page 73. If none of the CPs are configured for LVPECL operation, then the CPREF pin can be left unconnected.
CP Interface Signals
The C-3e NP's 8 external CPs support various network physical interfaces, providing a serial interface to the PHY layer. Interfaces are configured via bits in the C-3e NP register set. Many interfaces are possible by programming the configuration registers. CPs can be used individually or in a cluster (four CPs) to implement the various interfaces. Table 7 provides a quick reference of all the CP pins organized by clusters. There are seven physical I/O pins associated with each CP. All pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can be configured as differential pairs for LVPECL compatibility. In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for receive and four for transmit) or four CPs that share the transmit and receive functions for non-wire speed applications. During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the SDPs, with each getting access to the necessary I/O pins.
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The signals for the following CP physical interfaces are included in this section:
* * * * * *
DS1/T1 Framer Interface Configuration 10/100 Ethernet (RMII) Configuration Gigabit Ethernet (GMII) Configuration Gigabit Ethernet and Fibre Channel TBI Configuration SONET OC-3 Transceiver Interface Configuration SONET OC-12 Transceiver Interface Configuration
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Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters)
CP CLUSTER 1 SIGNAL PIN # CP CLUSTER 2 SIGNAL PIN #
CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP1_0 CP1_1 CP1_2 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 CP2_2 CP2_3 CP2_4 CP2_5 CP2_6 CP3_0 CP3_1 CP3_2 CP3_3 CP3_4
AG27 AF27 AE27 AD27 AC27 AB27 AG26 AE26 AC26 AB26 AG25 AF25 AE25 AD25 AC25 AB25 AG24 AF24 AD24 AB24 AG23 AF23 AE23 AD23 AC23 AB23
CP4_0 CP4_1 CP4_2 CP4_3 CP4_4 CP4_5 CP4_6 CP5_0 CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 CP6_0 CP6_1 CP6_2 CP6_3 CP6_4 CP6_5 CP6_6 CP7_0 CP7_1 CP7_2 CP7_3 CP7_4
AC22 AB22 AG21 AF21 AE21 AD21 AC21 AB21 AG20 AF20 AE20 AD20 AC20 AB20 AG19 AF19 AE19 AC19 AB19 AG18 AE18 AD18 AC18 AB18 AE17 AD17
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Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)
CP CLUSTER 1 SIGNAL PIN # CP CLUSTER 2 SIGNAL PIN #
CP3_5 CP3_6
AG22 AE22
CP7_5 CP7_6
AC17 AB17
DS1/T1 Framer Interface Configuration Table 8 describes the serial framer interface signals. For each CP (0-7), you can implement one serial Framer interface.
Table 8 DS1/T1 Framer Interface Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
TOTAL PINS
*
Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7
1 1 1 1 1 1 1 7
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc
OPD IPU OPD OPU IPD IPU ncPU
TCLK RCLK TData TFrame RData RFrame nc
Transmit Clock (1.544MHz) Receive Clock (1.544MHz) Transmit Data Transmit Frame Synchronization Receive Data Receive Frame Synchronization nc
n can be from 0 to 7. See Table 7. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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10/100 Ethernet (RMII) Configuration Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface (RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Table 9 10/100 Ethernet Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1
Table 7 Table 7
1 1
LVTTL LVTTL
OPD IPU
REF_CLK CRS_DV
CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
TOTAL PINS
*
Table 7 Table 7 Table 7 Table 7 Table 7
1 1 1 1 1 7
LVTTL LVTTL LVTTL LVTTL LVTTL
OPD OPU IPD IPU OPU
TXD(0) TXD(1) RXD(0) RXD(1) TX_EN
Transmit and Receive Clock (50MHz) Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... RX_DV indicates that a receive frame is in progress and the data present on the RXD pins is valid. It is asserted if this signal is a 1 for more than one cycle. Transmit Data 0 (first on wire) Transmit Data 1 (second on wire) Receive Data 0 (first on wire) Receive Data 1 (second on wire) Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable.
n can be from 0 to 7. See Table 7.
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Gigabit Ethernet (GMII) Configuration Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways:
* *
Use one CP cluster when density is more important than wire-speed performance because you can then implement up to four Gigabit Ethernet ports per C-3e NP. Use two CP clusters for wire-speed performance and additional processing power. You can implement up to two Gigabit Ethernet ports per C-3e NP.
Table 10 lists the possible CP cluster combinations you can use and Figure 4 shows receive and transmit pin configurations by cluster. Table 11 lists the signals and pinouts for Gigabit Ethernet (GMII).
Table 10 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel
CLUSTER SINGLE CLUSTER MODE (TBI OR GMII) TWO CLUSTER MODE (GMII)*
0 1
*
Port 1 Tx and Rx Port 2 Tx and Rx
Port 1 Tx Port 1 Rx
The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits.
Figure 4 GMII/TBI Transmit and Receive Pin Configurations
Single Cluster Mode Pin Configuration Tx Two Cluster Mode Pin Configuration
Cluster 0
Rx Tx
} Port 1 } Port 2
Tx
Cluster 0
Rx
nc
Tx
Cluster 1
Rx
Cluster 1
nc
Rx
}
Port 1
Cluster 2
NOTE: Cluster 2 & 3 are Internal Loopback Only.
Cluster 2
NOTE: Cluster 2 & 3 are Internal Loopback Only.
Cluster 3
Cluster 3 nc = not connected
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Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6
Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
OPD IPU OPD OPU OPD OPU OPU
T_CLK TCLKI TXD(0) TXD(1) TXD(2) TXD(3) TX_EN
GMII Transmit Clock (125MHz). This clock is used to synchronize the transmit data. MII transmit clock. Transmit data aligned to this clock input from phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable. nc Collision. Asserted when both RX_DV and TX_EN are valid during half duplex operation. Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide receive data, most significant bit) Transmit Error. Asserting TX_ER when TX_EN is a 1 causes transmission of the designated "bad code" in lieu of the normal encoded data on the twisted pair data. nc Receive Clock (125MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Receive Data Valid. Indicates that there is a receive frame in progress and that the data present on the RXD signals is valid. nc Carrier Sense. Indicates traffic is on the link. CRS is asserted when a non-idle condition is detected on the receive data stream. CRS is deasserted when an end of frame or idle condition is detected.
ncPD nc IPU OPD OPU OPD OPU OPU COL TXD(4) TXD(5) TXD(6) TXD(7) TX_ER
CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1
Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1
nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL
ncPD nc IPU IPD IPU IPD IPU IPU RCLK RXD(0) RXD(1) RXD(2) RXD(3) RX_DV
ncPD nc IPU CRS
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Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6
TOTAL PINS
*
Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 28
LVTTL LVTTL LVTTL LVTTL LVTTL
IPD IPU IPD IPU IPU
RXD(4) RXD(5) RXD(6) RXD(7) RX_ER
Receive Data Receive Data Receive Data Receive Data (most significant bit) Receive Error Detected. Indicates that there has been an error received in the receive frame.
n can be 0, or 4. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
Gigabit Ethernet and Fibre Channel TBI Configuration 1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same way as Gigabit Ethernet (GMII). Table 10 shows the possible CP pin combinations you can use and Figure 4 shows receive and transmit pin configurations by cluster. Table 12 shows the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI. The unused pins for the two cluster configurations should be wired down using a resistor.
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2
Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1
LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL
OPD ncPU OPD OPU OPD OPU OPU ncPD ncPU OPD
TCLK nc TXD(9) TXD(8) TXD(7) TXD(6) TXD(1) nc nc TXD(5)
Transmit Clock (125MHz). This clock is used to synchronize the transmit data. nc Transmit Data (ten bits wide, last on wire) Transmit Data Transmit Data Transmit Data Transmit Data nc nc Transmit Data
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Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1 CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6
TOTAL PINS
*
Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 Table 7 1 28
LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
OPU OPD OPU OPU ncPD IPU IPD IPU IPD IPU IPU ncPD IPU IPD IPU IPD IPU IPU
TXD(4) TXD(3) TXD(2) TXD(0) nc RCLK RXD(9) RXD(8) RXD(7) RXD(6) RXD(1) nc RCLKN RXD(5) RXD(4) RXD(3) RXD(2) RXD(0)
Transmit Data Transmit Data Transmit Data Transmit Data (ten bits wide, first on wire) nc Receive Clock (62.5 MHz) Receive Data (ten bits wide, last on wire) Receive Data Receive Data Receive Data Receive Data nc Receive Clock Inverted Receive Data Receive Data Receive Data Receive Data Receive Data (ten bits wide, first on wire)
n can be 0, or 4. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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SONET OC-3 Transceiver Interface Configuration Table 13 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each CP (0-15), you can implement a single OC-3 interface.
Table 13 OC-3 Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
TOTAL PINS
*
Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7
1 1 1 1 1 1 1 7
LVPECL IPD LVPECL IPU LVPECL OPD LVPECL IPU LVPECL IPD LVPECL IPU LVPECL IPU
RCLK_H RCLK_L TXD_H TXD_L RXD_H RXD_L SIGNAL_DET
Receive Clock noninverted side of pair (155.52MHz) Receive Clock inverted side of pair (155.52MHz) Transmit Data noninverted side of pair Transmit Data inverted side of pair Receive Data noninverted side of pair Receive Data inverted side of pair A light level above a certain threshold is present at the optical receiver - single ended LVPECL.
n can be from 0 to 7. Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
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SONET OC-12 Transceiver Interface Configuration SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a CP within a cluster spends half its time performing receive functions, and the other half performing transmit functions. Table 14 shows a CP Cluster configured for one OC-12 interface.
Table 14 OC-12 Signals Example
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0
Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7 Table 7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc
OPD IPU OPD OPU OPD OPU OPU ncPD ncPU OPD OPU OPD OPU ncPU ncPD IPU IPD IPU IPD IPU IPU ncPD
TCLK TCLKI TXD(0) TXD(1) TXD(2) TXD(3) 00F nc nc TXD(4) TXD(5) TXD(6) TXD(7) nc nc RCLK RXD(0) RXD(1) RXD(2) RXD(3) FP nc
Deskewed Transmit Clock (77.76MHz). This clock is used to synchronize the transmit data. Transceiver Transmit Clock. This clock sets the frequency of the transmit data and is typically sourced by the PHY chip. Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Out of Frame nc nc Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide data, most significant bit) nc nc Receive Clock (77.76MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Frame Synchronization Pulse. This is valid during the third A2 of the receive SONET frame. nc
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Table 14 OC-12 Signals Example (continued)
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn+3_1 CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6
TOTAL PINS
*
Table 7 Table 7 Table 7 Table 7 Table 7 Table 7
1 1 1 1 1 1 28
nc LVTTL LVTTL LVTTL LVTTL nc
ncPU IPD IPU IPD IPU ncPU
nc RXD(4) RXD(5) RXD(6) RXD(7) nc
nc Receive Data Receive Data Receive Data Receive Data (most significant bit) nc
n can be 0, or 4. Reference Table 7 for pin numbers for a different cluster.
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Executive Processor System Interface Signals
The XP's system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. It is also the primary interface used for initializing the C-3e NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM interface signals. PCI Signals The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or 66MHz. The PCI is fully compliant with PCI Specification revision 2.1. Table 15 describes the PCI signals.
Table 15 PCI Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
PAD0 - PAD31
AB9, AC9, AE9, AF9, AB8, AC8, AD8, AE8, AF8, AG8, AB7, AC7, AD7, AE7, AF7, AG7, AB6, AC6, AE6, AG6, AB5, AC5, AD5, AE5, AF5, AG5, AB4, AD4, AF4, AG4, AA3, AB3, AB2, AG3, AF3, AE3
32
PCI
I/O
Multiplexed Address/Data Bus. These signals are multiplexed address and data bits. The C-3e NP receives addresses as target and drives addresses as master. It drives the data and receives read data as master. Command byte enables. These signals are multiplexed command and byte enabled signals. The C-3e NP receives byte enables as target and drives byte enables as master. Parity. This signal carries even parity for AD and CBE# pins. It has the same receive and drive characteristics as the address and data bus, except that it is one PCI cycle later. Cycle frame Target ready for data transfer Initiator ready for data transfer Target transaction stop request Target device selected Bus parity error System error Bus clock Bus reset Initiator bus request (arbitration)
PCBEX0 - PCBEX3
4
PCI
I/O
PPAR
AG1
1
PCI
I/O
PFRAMEX PTRDYX PIRDYX PSTOPX PDEVSELX PPERRX PSERRX PCLK PRSTX PREQX
AA7 AB1 AC2 AE2 AG2 AC3 AD3 AF1 AE1 AD1
1 1 1 1 1 1 1 1 1 1
PCI PCI PCI PCI PCI PCI PCI IPD PCI PCI
I/O I/O I/O I/O I/O I/O I/O I I O
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Table 15 PCI Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
PGNTX PIDSEL PINTA
TOTAL PINS
AA8 AA5 AC1
1 1 1 50
IPD PCI PCI
I I O
Initiator bus grant (arbitration) Initialization device select Interrupt
Serial Interface Signals The Serial interface is a bidirectional two-wire serial bus. It can use one of the following formats:
* *
An 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols. Which of the two data rates used is selected by the state of the PROM interface's SPLD signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is selected. The bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
Table 16 Serial Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
SICL SIDA
TOTAL PINS
AA1 AA4
1 1 2
LVTTL LVTTL
IPD/O Serial Clock line IPD/O Serial Data line
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PROM Interface Signals The PROM interface is a low speed I/O port that allows the C-3e NP to communicate through external logic to PROM. The PROM clock is 1/2 to 1/16 the core clock rate.The maximum PROM size addressable is 4MBytes, and must use a "by 16" part. The PROM signals are listed in Table 17.
Table 17 PROM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
SPDO SPDI SPLD
Y5 Y6 Y7
1 1 1
LVTTL LVTTL LVTTL
O IPD O
Serial Data Out Serial Data In When load is asserted on a positive clock edge, the external logic performs a parallel load. On each positive clock edge when load is de-asserted, the shift registers shift. When the PROM interface is idle: * if SPLD is asserted HI it indicates low speed serial protocol,
*
SPCK
TOTAL PINS
if asserted LOW it indicates MDIO serial protocol.
Y8
1 4
LVTTL
O
Clock
Figure 5 shows the connections between the PROM Interface and external board logic. The application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. Both devices should be positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When SPLD is deasserted the shift register shifts.
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Figure 5 PROM Interface Diagram
21
C-3e Network Processor
0 PROM_ADDR<21:1> 21
CE
External Logic
SPDO
21
6
1 0 SPDI
21
60
15 31 16 PROM _H_Word PROM _Return_Data 15
Internal Shift Register 21 0
External Shift Register 0
CE
PROM_ADDR<21:1>
PROM _LO_Word 21 PROM Clock Gen. SPCLK PROM Sequencer SPLD PROM PROM_Data 1 16
The PROM interface operates in the following manner (Note that two accesses are piplined together to execute one 32-bit fetch). The steps are shown in Figure 6. 1 The PROM_ADDR is loaded into the network processor internal shift register. 2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles. 3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register. 4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift register. 5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register and the first PROM_DATA into the external shift register. 6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network processor internal shift register. 7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network processor PROM_RETURN_DATA register and the second PROM_DATA into the external shift register.
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8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the network processor internal shift register. 9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the network processor PROM_RETURN_DATA register.
Figure 6 PROM Interface Timing Outline
XP PROM Interface outline SPLD SPDTO
Q< Q< Q< Q<
`
A5
A1
A2
A3
A4
SPDTI XP PROM Interface detail
1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9
D1
D2
D3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
SPCLK SPLD SPDTO
x
A1
AAAAAAAAAAAA 20 19 18 17 16 15 14 13 12 11 10 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A CE 0
A2
A3
A4
1
The PROM_ADDR is loaded into the C-5's internal shift register. The PROM_ADDR is shifted into the external shift register. (SPCLK Rising Edge used for shifting)
3
5 4
The PROM_DATA is loaded into the external shift register. D1
x DDDDDDD 15 14 13 12 11 10 9 D 8 D 7 D 6 D 5 DD 43 D 2 D 1 D 0 x x x x x x
2
The PROM_ADDR is loaded into the external presentation register. The PROM_DATA is presenting.
D2
SPDTI
6
8 7
The PROM_DATA is shifted into the C-5's Internal shift register.
9
The PROM_DATA is loaded into the C-5's internal PROM_RETURN_DATA register.
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General System Interface Signal Table 18 provides the signal for the Executive Processor reset power status and I/O clock. The C-3e NP can be powered up with the XP either running or with the XP in reset mode similar to the CPs. When the XP remains in reset mode, an external host can be used to control the initialization of the C-3e NP.
Table 18 General System Interface Signal
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
XPUHOT
Y3
1
LVTTL
IPD
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low equals reset and High equals active. During normal operation, this is an external interrupt.
TOTAL PINS
1
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Fabric Processor Interface Signals
The FP has logical signal interfaces: a receive data interface and a transmit data interface, each with its own control, data, and clock signals. The interface has the following characteristic: The interface clocks FRXCLK and FTXCLK can have a different frequency from the core C-3e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to 125MHz. FRXCLK and FTXCLK can be independent of each other; typically they have the same frequency, but are allowed to be skewed relative to each other. Each data bus can be configured for widths of 8 (data bits 7:0 are used), or 16 (bits 15:0). In 8bit mode, data bits 15:8 are unused.
Table 19 Fabric Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
FIN0 - FIN15
AD13, AC13, AB13, AG12, AF12, AE12, AD12, AC12, AB12, AG11, AF11, AE11, AD11, AC11, AB11, AG10 AG17, AF17, AG16, AF16, AE16, AD16, AC16, AB16, AG15, AF15, AE15, AD15, AC15, AB15, AG14, AE14 AG9 AE13
16
LVTTL
IPD
Fabric Data Bus In
FOUT0 - FOUT15
16
LVTTL
O
Fabric Data Bus Out
FRXCLK FTXCLK
1 1 4 4 42
LVTTL LVTTL LVTTL LVTTL
IPD IPD
Receive Clock Transmit Clock
FRXCTL0 - FRXCTL2 & AE10, AD10, AC10, AB10 FRXCTL6 FTXCTL0 - FRXCTL2 & AC14, AB14, AG13, AF13 FTXCTL6
TOTAL PINS
IPD, O Receive Control Signals IPD, O Transmit Control Signals
The following tables list the Fabric Interface pin mappings:
* *
Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 20 Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 21
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Table 20 Utopia1*, 2*, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS C-3E NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-3E NETWORK PROCESSOR I/O UTOPIA NOTE
FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL6
*
Output Input Input Input
RxEnb* RxClav RxSOC RxPrty
Pullup or No Connection
FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL6
Output Input Output Output
TxEnb* TxClav TxSOC TxPrty
Pullup or No Connection
Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low.
Table 21 Utopia1*, 2*, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS C-3E NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-3E NETWORK PROCESSOR I/O UTOPIA NOTE
FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL6
*
Input Output Input Input
TxEnb* TxClav TxSOC TxPrty
Pullup No Connection
FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL6
Input Output Output Output
RxEnb* RxClav RxSOC RxPrty
Pullup No Connection
Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low.
When configuring two C-3e network processors back-to-back using the Fabric Port, set up the transmit side of each C-3e network processor in Utopia ATM mode and the receive side of each C-3e network processor in Utopia PHY mode.
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BMU SDRAM Interface Signals
The BMU and SDRAM interface signals are described in Table 22. The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines and all 12 address lines must be connected to the SDRAM in order for the BMU to be able to read and write external SDRAM properly.
Table 22 BMU SDRAM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
MD0 - MD129
AA27, AA25, AA24, AA23, AA21, 130 AA20, Y27, Y26, Y25, Y23, Y22, Y21, Y20, W27, W26, W25, W23, W22, W21, W20, V27, V25, V24, V23, V21, V20, U27, U26, U25, U24, U23, U22, U21, U20, T27, T26, T25, T23, T22, T21, T20, R27, R26, R25, R24, R23, R22, R21, R20, P27, P25, P24, P23, P21, P20, N27, N26, N25, N24, N23, N22, N21, N20, M27, M26, M25, M23, M22, M21, M20, L27, L26, L25, L24, L23, L22, L21, L20, K27, K25, K24, K23, K21, K20, J27, J26, J25, J23, J22, J21, J20, H27, H26, H25, H23, H22, H21, H20, G27, G25, G24, G23, G21, G20, F27, F26, F25, F24, F23, F22, F21, F20, E27, E26, E25, E23, E22, E21, E20, D27, D25, D24, D23, D21, D20, C27, C26, C25, C23, C22 9 12
LVTTL
IPD/O Data Lines In
MDECC0 - MDECC8 A27, B20, B21, B23, B24, B25, B27, C20, C21 MA0 - MA11 C19, B19, A19, F18, E18, D18, C18, A18, F17, E17, D17, C17
LVTTL LVTTL
IPD/O Stored as data, ECC bits OPD Address Outputs: A0-A11 are sampled during the ACTIVE command and READ/WRITE to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a LOAD MODE REGISTER command Bank Address Outputs: BA0 and BA1 define which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. NOTE: MCSX is considered part of the command code.
MBA0 - MBA1
F19, E19
2
LVTTL
OPD
MCASX
A24
1
LVTTL
OPD
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Table 22 BMU SDRAM Interface Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
MRASX
A23
1
LVTTL
OPD
Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Chip Select: MCSX enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when MCSX is registered HIGH. MCSX provides the external bank selection on systems with multiple banks. MCSX is considered part of the command code. Input/Output Mask: MDQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when MDQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a high Z state (two-clock latency) when MDQM is sampled HIGH during the READ cycle. NOTE: MDQML is an identical copy of MDQM used to drive the loading on SDRAM configurations with 2 DQM pins. Clock: MDCLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of the MDCLK. MDCLK also increments the internal burst counter and controls the output registers.
MWEX
A22
1
LVTTL
OPD
MCSX
A25
1
LVTTL
OPD
MDQM MDQML
A20 A21
1 1
LVTTL LVTTL
OPD OPD
MDCLK
A26
1
LVTTL
IPD
TOTAL PINS
160
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TLU SRAM Interface Signals
The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 125MHz using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to 64Mbits. The TLU SRAM interface signals are described in Table 23.
Table 23 TLU SRAM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
TD0 - TD63
F3, F4, F5, F6, F7, F8, G1, G3, G4, G5, G7, G8, H1, H2, 64 H3, H5, H6, H7, H8, J1, J2, J3, J5, J6, J7, J8, K1, K3, K4, K5, K7, K8, L1, L2, L3, L4, L5, L6, L7, L8, M1, M2, M3, M5, M6, M7, M8, N1, N2, N3, N4, N5, N6, N7, N8, P1, P3, P4, P5, P7, P8, R1, R2, R3 U2, U3, U4, U5, U6, U7, U8, V1, V3, V4, V5, V7, V8, W1, W2, W3, W5, W6, W7, W8, Y1, Y2 T1, T2, T3, T5 T6, T7, T8, U1 R5, R6, R7, R8 R4 22 4 4 4 1 99
LVTTL
IPD/O TLU Memory Data
TA0 - TA21 TPAR0 - TPAR3 TCE0X - TCE3X TWE0X - TWE3X TCLKI
TOTAL PINS
LVTTL LVTTL LVTTL LVTTL LVTTL
OPD
TLU Memory Address
IPD/O Word Data Parity (i.e. TPAR0 across TD15:0) OPD OPD IPD TLU Memory Chip Enable TLU Memory Write Enable TLU Clock Input
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QMU SRAM (Internal Mode) Interface Signals
The QMU signals are described in Table 24.
Table 24 QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
QA0 - QA16 QD0 - QD31
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12, E12, D12, C12, A12, F13, E13, D13
17
LVTTL LVTTL
O
Address [16:0]
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, 32 D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7, C7, B7, A7, E8, D8 C8 F10 A9 E10 B8 A8 F9 E9 C9 B9 1 1 1 1 1 1 1 1 1 1 59
IPD/O Data
QDQPAR QARDY QNQRDY QWEX QBCLKO QBCLKI QACLKO QACLKI QDPL QDPH
TOTAL PINS
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
IPD IPD IPD O O IPD O IPD
nc nc nc Write Enable nc nc nc Input Clock
IPD/O Data Parity Low IPD/O Data Parity High
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55
QMU to Q-5/Q-3 (External Mode) Interface Signals
The QMU to Q-5/Q-3 signals are described in Table 25.
Table 25 QMU to Q-5/Q-3 (External Mode) Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
QA0 - QA15 QA16 QD0 - QD23 QD24 - QD31 QDQPAR QARDY QNQRDY QWEX QBCLKO QBCLKI QACLKO QACLKI QDPL QDPH
TOTAL PINS
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12, E12, D12, C12, A12, F13, E13 D13 F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, D4, B4, A4, E5, D5, C5, B5, A5, E6, C6 A6, E7, D7, C7, B7, A7, E8, D8 C8 F10 A9 E10 B8 A8 F9 E9 C9 B9
16 1 24 8 1 1 1 1 1 1 1 1 1 1 59
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
O O IPD IPD IPD IPD O O O IPD O IPD O O
Enqueue Data [8:23] Enqueue Parity Dequeue Data [0:23] Enqueue Data [0:7] Dequeue Parity Dequeue Ack Ready Enqueue Ready Dequeue Ready Output ClockB Input ClockB Output ClockA Input ClockA Dequeue Ack [0] Dequeue Ack [1]
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Power Supply Signals
Table 26 Power Supply Signals
SIGNAL NAME PIN #
Power supply, and ground signals are described in Table 26.
TOTAL
TYPE
SIGNAL DESCRIPTION
VDD
H10, H12, H16, J11, J13, J15, J17, K10, K12, K14, K16, 57 K18, L11, L13, L15, L17, M10, M12, M14, M16, M18, N11, N13, N15, N17, P10, P12, P14, P16, P18, R11, R13, R15, R17, T10, T12, T14, T16, T18, U11, U13, U15, U17, V10, V12, V14, V16, V18, W11, W13, W15, W17, Y10, Y12, Y14, Y16, Y18 B18, B26, C24, D14, D22, G13, G15, G17, G19, G26, 40 H14, H18, H24, J19, K22, L19, M24, N19, P26, R19, U19, V22, W19, W24, AA9, AA11, AA13, AA15, AA17, AA19, AA26, AD6, AD14, AD22, AE4, AE24, AF2, AF10, AF18, AF26 B6, B12, B16, B22, D2, D9, D19, D26, E4, E24, G6, G10, 117 G12, G14, G16, G18, G22, H9, H11, H13, H15, H17, H19, J4, J10, J12, J14, J16, J18, J24, K2, K9, K11, K13, K15, K17, K19, K26, L10, L12, L14, L16, L18, M9, M11, M13, M15, M17, M19, N10, N12, N14, N16, N18, P6, P9, P11, P13, P15, P17, P19, P22, R10, R12, R14, R16, R18, T4, T9, T11, T13, T15, T17, T19, T24, U10, U12, U14, U16, U18, V2, V9, V11, V13, V15, V17, V19, V26, W10, W12, W14, W16, W18, Y4, Y9, Y11, Y13, Y15, Y17, Y19, Y24, AA6, AA10, AA12, AA14, AA16, AA18, AA22, AC4, AC24, AD2, AD9, AD19, AD26, AF6, AF14, AF22 B2, B10, C4, D6, G2, G9, G11, H4, J9, K6, L9, M4, N9, P2, R9, U9, V6, W4, W9, AA2 20 234
P
Core Supply Voltage (1.1V Input)
VDD33
P
I/O Supply Voltage (3.3V Input)
GND
P
Ground
VDDT
TOTAL PINS
P
TLU and QMU I/O supply (3.3V)
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57
Test Signals
Test signals are described in Table 27.
Table 27 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
JTCK JTMS
B17 A17
1 1
LVTTL LVTTL
IPD IPD
Test Clock Test Mode Select. High selects modes as defined in the IEEE 1149.1 JTAG specification. Test Reset (low active) Test Data In Test Data Out Turns off all output drivers when High 1X or 2X Clock Mode Select. Low selects 1X, High selects 2X. Scan Enable. High enables scan test. Scan Out Pins
JTRSTX JTDI JTDO JHIGHZ JCLKBYP JSE JS00-JS05
TOTAL PINS
A16 C16 C14 B15 A15 D15 C13, B13, A13, B14, A14, C15
1 1 1 1 1 1 6 14
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
IPD IPD O IPD IPD IPD O
During JTAG, SCLK and SCLKX must remain as differential inputs.
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Signals Grouped by Pin Number
The C-3e NP signals are listed by pin number in Table 28.
Table 28 Signals Listed by Pin Number
PIN FUNCTION PIN FUNCTION PIN A 1-27 FUNCTION PIN FUNCTION
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6
Not present QD8 QD13 QD16 QD21 QD24 QD29 QBCLKI QD4 VDDT QD12 QD15 QD20 GND QD28 QBCLKO QD3 QD7 QD11 VDDT QD19 QD23
A9 A10 A11 A12 A13 A14 A15 A16 B9 B10 B11 B12 B13 B14 B15 B16 C9 C10 C11 C12 C13 C14
QNQRDY QA2 QA8 QA13 JS02 JS04 JCLKBYP JTRSTX QDPH VDDT QA7 GND JS01 JS03 JHIGHZ GND QDPL QA1 QA6 QA12 JS00 JTDO
A17 A18 A19 A20 A21 A22 A23 A24
B 1-27
JTMS MA7 MA2 MDQM MDQML MWEX MRASX MCASX JTCK VDD33 MA1 MDECC1 MDECC2 GND MDECC3 MDECC4 MA11 MA6 MA0 MDECC7 MDECC8 MD129
A25 A26 A27
MCSX MDCLK MDECC0
B17 B18 B19 B20 B21 B22 B23 B24
C 1-27
B25 B26 B27
MDECC5 VDD33 MDECC6
C17 C18 C19 C20 C21 C22
C25 C26 C27
MD127 MD126 MD125
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59
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
C7 C8 D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6
QD27 QDQPAR QD2 GND QD10 QD14 QD18 VDDT QD26 QD31 QD1 QD6 QD9 GND QD17 QD22 QD25 QD30 QD0 QD5 TD0 TD1 TD2 TD3
C15 C16 D9 D10 D11 D12 D13 D14 D15 D16 E9 E10 E11 E12 E13 E14 E15 E16 F9 F10 F11 F12 F13 F14
JS05 JTDI GND QA0 QA5 QA11 QA16 VDD33 JSE CPREF QACLKI QWEX QA4 QA10 QA15 CCLK3 CCLK2 CCLK1 QACLKO QARDY QA3 QA9 QA14 SCLK
C23 C24
D 1-27
MD128 VDD33 MA10 MA5 GND MD124 MD123 VDD33 MD122 MD121 MA9 MA4 MBA1 MD118 MD117 MD116 MD115 GND MA8 MA3 MBA0 MD111 MD110 MD109 F25 F26 F27 MD106 MD105 MD104 E25 E26 E27 MD114 MD113 MD112 D25 D26 D27 MD120 GND MD119
D17 D18 D19 D20 D21 D22 D23 D24
E 1-27
E17 E18 E19 E20 E21 E22 E23 E24
F 1-27
F17 F18 F19 F20 F21 F22
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Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
F7 F8 G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 J1 J2 J3 J4 J5 J6
TD4 TD5 TD6 VDDT TD7 TD8 TD9 GND TD10 TD11 TD12 TD13 TD14 VDDT TD15 TD16 TD17 TD18 TD19 TD20 TD21 GND TD22 TD23
F15 F16 G9 G10 G11 G12 G13 G14 G15 G16 H9 H10 H11 H12 H13 H14 H15 H16 J9 J10 J11 J12 J13 J14
SCLKX CCLK0 VDDT GND VDDT GND VDD33 GND VDD33 GND GND VDD GND VDD GND VDD33 GND VDD VDDT GND VDD GND VDD GND
F23 F24
G 1-27
MD108 MD107 VDD33 GND VDD33 MD103 MD102 GND MD101 MD100 GND VDD33 GND MD97 MD96 MD95 MD94 VDD33 VDD GND VDD33 MD90 MD89 MD88 J25 J26 J27 MD86 MD85 MD84 H25 H26 H27 MD93 MD92 MD91 G25 G26 G27 MD99 VDD33 MD98
G17 G18 G19 G20 G21 G22 G23 G24
H 1-27
H17 H18 H19 H20 H21 H22 H23 H24
J 1-27
J17 J18 J19 J20 J21 J22
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61
Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
J7 J8 K1 K2 K3 K4 K5 K6 K7 K8 L1 L2 L3 L4 L5 L6 L7 L8 M1 M2 M3 M4 M5 M6 M7
TD24 TD25 TD26 GND TD27 TD28 TD29 VDDT TD30 TD31 TD32 TD33 TD34 TD35 TD36 TD37 TD38 TD39 TD40 TD41 TD42 VDDT TD43 TD44 TD45
J15 J16 K9 K10 K11 K12 K13 K14 K15 K16 L9 L10 L11 L12 L13 L14 L15 L16 M9 M10 M11 M12 M13 M14 M15
VDD GND GND VDD GND VDD GND VDD GND VDD VDDT GND VDD GND VDD GND VDD GND GND VDD GND VDD GND VDD GND
J23 J24
K 1-27
MD87 GND GND VDD GND MD83 MD82 VDD33 MD81 MD80 VDD GND VDD33 MD77 MD76 MD75 MD74 MD73 GND VDD GND MD69 MD68 MD67 MD66 M25 M26 M27 MD65 MD64 MD63 L25 L26 L27 MD72 MD71 MD70 K25 K26 K27 MD79 GND MD78
K17 K18 K19 K20 K21 K22 K23 K24
L 1-27
L17 L18 L19 L20 L21 L22 L23 L24
M 1-27
M17 M18 M19 M20 M21 M22 M23
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Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
M8 N1 N2 N3 N4 N5 N6 N7 N8 P1 P2 P3 P4 P5 P6 P7 P8 R1 R2 R3 R4 R5 R6 R7
TD46 TD47 TD48 TD49 TD50 TD51 TD52 TD53 TD54 TD55 VDDT TD56 TD57 TD58 GND TD59 TD60 TD61 TD62 TD63 TCLKI TWE0X TWE1X TWE2X
M16 N9 N10 N11 N12 N13 N14 N15 N16 P9 P10 P11 P12 P13 P14 P15 P16 R9 R10 R11 R12 R13 R14 R15
VDD VDDT GND VDD GND VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD VDDT GND VDD GND VDD GND VDD
M24
N 1-27
VDD33 VDD GND VDD33 MD62 MD61 MD60 MD59 MD58 GND VDD GND MD54 MD53 GND MD52 MD51 VDD GND VDD33 MD48 MD47 MD46 MD45 R25 R26 R27 MD43 MD42 MD41 P25 P26 P27 MD50 VDD33 MD49 N25 N26 N27 MD57 MD56 MD55
N17 N18 N19 N20 N21 N22 N23 N24
P 1-27
P17 P18 P19 P20 P21 P22 P23 P24
R 1-27
R17 R18 R19 R20 R21 R22 R23
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Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
R8 T1 T2 T3 T4 T5 T6 T7 T8 U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8
TWE3X TPAR0 TPAR1 TPAR2 GND TPAR3 TCE0X TCE1X TCE2X TCE3X TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 GND TA8 TA9 TA10 VDDT TA11 TA12
R16 T9 T10 T11 T12 T13 T14 T15 T16 U9 U10 U11 U12 U13 U14 U15 U16 V9 V10 V11 V12 V13 V14 V15 V16
GND GND VDD GND VDD GND VDD GND VDD VDDT GND VDD GND VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD
R24
T 1-27
MD44 GND VDD GND MD40 MD39 MD38 MD37 GND VDD GND VDD33 MD33 MD32 MD31 MD30 MD29 GND VDD GND MD25 MD24 VDD33 MD23 MD22 V25 V26 V27 MD21 GND MD20 U25 U26 U27 MD28 MD27 MD26 T25 T26 T27 MD36 MD35 MD34
T17 T18 T19 T20 T21 T22 T23 T24
U 1-27
U17 U18 U19 U20 U21 U22 U23 U24
V 1-27
V17 V18 V19 V20 V21 V22 V23 V24
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Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN W 1-27 FUNCTION PIN FUNCTION
W1 W2 W3 W4 W5 W6 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8
TA13 TA14 TA15 VDDT TA16 TA17 TA18 TA19 TA20 TA21 XPUHOT GND SPDO SPDI SPLD SPCK SICL VDDT PAD30 SIDA PIDSEL GND PFRAMEX PGNTX
W9 W10 W11 W12 W13 W14 W15 W16 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16
VDDT GND VDD GND VDD GND VDD GND GND VDD GND VDD GND VDD GND VDD VDD33 GND VDD33 GND VDD33 GND VDD33 GND
W17 W18 W19 W20 W21 W22 W23 W24
Y 1-27
VDD GND VDD33 MD19 MD18 MD17 MD16 VDD33 GND VDD GND MD12 MD11 MD10 MD9 GND VDD33 GND VDD33 MD5 MD4 GND MD3 MD2
W25 W26 W27
MD15 MD14 MD13
Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24
AA 1-27
Y25 Y26 Y27
MD8 MD7 MD6
AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24
AA25 AA26 AA27
MD1 VDD33 MD0
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Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN AB 1-27 FUNCTION PIN FUNCTION
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
PTRDYX PCBEX0 PAD31 PAD26 PAD20 PAD16 PAD10 PAD4 PINTA PIRDYX PPERRX GND PAD21 PAD17 PAD11 PAD5 PREQX GND PSERRX PAD27 PAD22 VDD33 PAD12 PAD6
AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16
PAD0 FRXCTL6 FIN14 FIN8 FIN2 FTXCTL1 FOUT13 FOUT7 PAD1 FRXCTL2 FIN13 FIN7 FIN1 FTXCTL0 FOUT12 FOUT6 GND FRXCTL1 FIN12 FIN6 FIN0 VDD33 FOUT11 FOUT5
AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
AC 1-27
CP7_6 CP7_2 CP6_4 CP5_6 CP5_0 CP4_1 CP3_4 CP2_5 CP7_5 CP7_1 CP6_3 CP5_5 CP4_6 CP4_0 CP3_3 GND CP7_4 CP7_0 GND CP5_4 CP4_5 VDD33 CP3_2 CP2_4
AB25 AB26 AB27
CP2_1 CP1_2 CP0_5
AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24
AD 1-27
AC25 AC26 AC27
CP2_0 CP1_1 CP0_4
AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24
AD25 AD26 AD27
CP1_6 GND CP0_3
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Table 28 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN AE 1-27 FUNCTION PIN FUNCTION
AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8
PRSTX PSTOPX PCBEX3 VDD33 PAD23 PAD18 PAD13 PAD7 PCLK VDD33 PCBEX2 PAD28 PAD24 GND PAD14 PAD8 PPAR PDEVSELX PCBEX1 PAD29 PAD25 PAD19 PAD15 PAD9
AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16
PAD2 FRXCTL0 FIN11 FIN5 FTXCLK FOUT15 FOUT10 FOUT4 PAD3 VDD33 FIN10 FIN4 FTXCTL6 GND FOUT9 FOUT3 FRXCLK FIN15 FIN9 FIN3 FTXCTL2 FOUT14 FOUT8 FOUT2
AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24
AF 1-27
CP7_3 CP6_6 CP6_2 CP5_3 CP4_4 CP3_6 CP3_1 VDD33 FOUT1 VDD33 CP6_1 CP5_2 CP4_3 GND CP3_0 CP2_3 FOUT0 CP6_5 CP6_0 CP5_1 CP4_2 CP3_5 CP2_6 CP2_2
AE25 AE26 AE27
CP1_5 CP1_0 CP0_2
AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24
AG 1-27
AF25 AF26 AF27
CP1_4 VDD33 CP0_1
AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24
AG25 AG26 AG27
CP1_3 CP0_6 CP0_0
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JTAG Support
67
JTAG Support
The C-3e NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All required public instructions are implemented, as well as some optional instructions. This section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types.
Pinout
The C-3e NP uses the standard JTAG pins including the optional test reset pin. Table 27 describes the pins and their functions. The C-3e NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in Table 29.
Table 29 JTAG Internal Register Descriptions
REGISTER NAME REGISTER LENGTH DESCRIPTION
JTAG Data Registers
Bypass Boundary Device Identification
1 1549 32
Standard JTAG bypass register Boundary Scan Register Standard JTAG IDCODE Register
Boundary Scan Restriction Boundary Scan Cell Types
SCLK/SCLKX inputs must not toggle when exercising the boundary scan function for JTAG. The C-3e NP boundary scan register contains only two cell types. All input cells are observe only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE 1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in Figure 8.
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CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 7 Observe-Only Cell
To next cell
From System Pin G1 0 1 From last cell Shift DR Clock DR
To System Logic
1D C1
Figure 8 Cell Design That Can Be Used for Both Input and Output Pins
Node To next cell G1 0 1 G1 0 1 From last cell Clock DR From/To System
Shift DR To/From System Pin
1D C1
1D C1 Update DR
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IDcode Register
The C-3e NP implements a standard 32bit JTAG identification register. Table 30 lists the value of the code for full identification and its sub-components.
Table 30 JTAG Identification Code and Its Sub-components
FIELD NAME WIDTH BIT POSITIONS BINARY VALUE
Version Part Number Manufacturer Identity LSB
4 16 11 1
31-28 27-12 11-1 0
0000 0000_0000_0010_0001 001_1001_0110 1
The concatenated 32bit value is hexidecimal 0002132d.
JTAG Instruction Register
The C-3e NP contains a 4bit instruction register. Table 31 lists the instructions that are supported.
Table 31 Instruction Register Instructions
INSTRUCTION MNEMONIC SELECTED REGISTER INSTRUCTION OPCODE
Extest Idcode Sample/Preload Highz Clamp Bypass Reserved* Reserved* Bypass Bypass Bypass Bypass Bypass Bypass
Boundary Scan Identification Register Boundary Scan Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101
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Table 31 Instruction Register Instructions (continued)
INSTRUCTION MNEMONIC SELECTED REGISTER INSTRUCTION OPCODE
Bypass Bypass
*
Bypass Register Bypass Register
1110 1111
There are two reserved instructions intended for Motorola Corporation's internal use. These should not be programmed by users.
Boundary Scan Description Language
In order to simplify board test, Motorola Corporation has provided a boundary scan description language (BSDL) file (c3e.bsdl) in the Motorola web site that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. http://www.motorola.com/networkprocessors
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Table 32 lists the absolute maximum ratings for the C-3e network processor. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" (Table 33) is possible. Exposure to conditions beyond Table 32 can:
* *
Reduce device reliability Result in premature device failure, even with no immediate sign of failure
Prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the C-3e NP.
Table 32 C-3e Network Processor Absolute Maximum Ratings
PARAMETER MIN MAX UNIT
VDD33/VDDT Supply Voltage (3.3V input)* VDD Supply Voltage (1.1V input)* Voltage on any pin Static Discharge Voltage Storage Temperature Absolute Maximum Junction Temperature
*
-0.5 -0.5 -0.5 2000/500 -40 -40
+5 +2.2 VDD33 + 0.5 +125 +125
V V V V C C
Voltages are relative to Ground
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Recommended Operating Conditions
The recommended operating conditions describe an environment the C-3e NP network processor is expected to encounter during normal operation. Table 33 delineates the recommended operating parameters for the C-3e NP.
Table 33 C-3e Network Processor Recommended Operating Conditions
PARAMETER MIN NOMINAL MAX UNIT
VDD33 Supply Voltage VDDT Supply Voltage VDD Supply Voltage IDD33 - VDD33 Supply Current IDD - VDD Supply Current Tj Junction Temperature
3.135 3.135 1.04
3.3 3.3 1.2
3.465 3.465 1.16 0.6 5.0
V V V A A C
-40
125
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DC Characteristics
73
DC Characteristics
The DC electrical characteristics define the input operating conditions for proper operation and the output responses to applied DC signals and switch characteristics over specified voltage and temperature ranges. The DC electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. Table 34 outlines the C-3e NP DC characteristics.
Table 34 C-3e Network Processor DC Characteristics
PARAMETER* MIN MAX UNIT NOTES
LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Output High Voltage LVTTL Output Low Voltage LVTTL Input Current LVPECL Input High Voltage LVPECL Input Low Voltage LVPECL Output High Voltage LVPECL Output Low Voltage LVPECL Input Current CPREF
*
2.0 -0.3 2.4
VDD33+.3 0.8 0.4
V V V V @IOH = -2mA @IOL = +2mA VIN = 0V or VDD33
-100 VDD33 -1.165 -0.3 VDD33 -1.025 VDD33 -2.20 -100 VDD33 -1.38
+100 VDD33+.3V VDD33 -1.475 VDD33 -0.60 VDD33 -1.620 +100 VDD33 -1.26
A
V V V V
Load = 50ohm to VDD33 - 2V Load = 50ohm to VDD33 - 2V Single-ended LVPECL reference
A
V
All voltages are relative to Ground unless otherwise indicated.
Each control input pin has a capacitance associated with it. The capacitance at the control input is due to the package and the input circuitry connected to the pin. Capacitance is based on these conditions: TA = 25C; VDD33 = 3.3V; f = 1MHz. Table 35 provides capacitance data.
Table 35 C-3e Network Processor Capacitance Data
PARAMETER TYPICAL UNIT
All Pins
5
pF
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Power Sequencing
It is intended that the VDD33/VDDT and VDD rails are sequenced to their final value together for most applications. VDD33 and VDDT must be above VDD at all times. VDD must be brought to its final value within 100ms of sequencing on VDD33 and VDDT. It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running or begin running during power sequencing to propagate reset inside the C-3e NP. Figure 9 indicates the relationship between the clocks and PRSTX. There is no requirement that the asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be asserted within 100s of power initiation. Typically, reset is held low during power initiation.
Figure 9 Bringup Clock Timing Diagram
VDD, VDD33, VDDT
100s
PRSTX
)(
1ms
TCLKI, PCLK, SCLK, SCLKX, MDCLK, FTXCLK, FRXCLK
100s
)(
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Power and Thermal Characteristics
Table 36 provides the derived power and thermal characteristics for the production version of the C-3e NP.
Table 36 C-3e Network Processor Power and Thermal Characteristics
PARAMETER MIN TYP MAX UNITS TEST CONDITIONS
Power Dissipation, PD Maximum Junction Temperature, TJ Thermal Resistance, junction to case, JC Thermal Resistance, junction to printed circuit board, JB
2.5
5.5
7.5 125
W
oC oC/W oC/W
180MHz core clock See Note below See Note below See Note below See Note below
<0.1 5.5
Table 36 note: Power dissipation values assume the following conditions:
* * * * * * *
Thermal Management Information
BMU memory operating at 125MHz TLU memory operating at 125MHz QMU operating at 150MHz VDD = 1.1V, VDD33/VDDT = 3.3V, TJ at approximately 50C for typical values. VDD and VDD33/VDDT are 5% higher for maximum values "Minimum" PD based on idle condition (clocks running and no programs executing) "Typical" PD based on test application that implements Fast Ethernet forwarding actively running on all CPs "Maximum" PD based on maximum consumption for any high-bandwidth communications application executing on all CPs, FP, and XP
This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods--spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (refer to Figure 10); however, due to the potential
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large mass of the heat sink, attachment through the printed circuit board is suggested. If a spring clip is used, the spring force should not exceed 5.5 pounds.
Figure 10 Package Cross Section View with Serveral Heat Sink Options
Heat Sink
Heat Sink Clip
Thermal Interface Material
CBGA Package
Printed Circuit Board
Internal Package Conduction Resistance For the exposed-die packaging technology the intrinsic conduction thermal resistance paths are as follows:
* *
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance The die junction-to-ball thermal resistance
Figure 11 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
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Figure 11 Package with Heat Sink Mounted to the Printed Circuit Board
External Resistance Radiation Convection
Heat Sink
Thermal Interface Material
Internal Resistance
Die/Package Die Junction Package/Leads
Printed Circuit Board (PCB)
External Resistance
Radiation
Convection
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by convection. Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: T j = T a + T r + (jc + int + sa ) x P d where: T j is the die-junction temperature T a is the inlet cabinet ambient temperature T r is the air temperature rise within the computer cabinet
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jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance
P d is the power dissipated by the device During operation, the die-junction temperatures (T j ) should be maintained less than the value specified in Table 36. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a ) may range from 30 to 40C. The air temperature rise within a cabinet (T r ) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (int ) is typically about 1.5C/W. For example, assuming a T a of 30C, a T r of 5C, a CBGA package jc = 0.1, and a maximum power consumption (P d ) of 7.5 W, the following expression for T j is obtained: Die-junction temperature: T j = 30C + 5C + (0.1C/W + 1.5C/W + sa ) x 7.5 W For this example, a sa value of 10.4C/W or less is required to maintain the die junction temperature below the maximum value of Table 36. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs.
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AC Timing Specifications
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AC Timing Specifications
AC timing specifications consist of input requirements and output responses. The input requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal. The AC timing specifications are defined separately for each interface to the C-3e NP. See Figure 12. Output timing specifications for LVTTL pins are given with a 20pF load on the output. Other loads can be simulated with the IBIS model available from Motorola. The LVPECL driver is specified into a 50 load terminated to a (VDD33 - 2V) reference.
Figure 12 Test Loading Conditions
LVTTL DUT 20pF
VDD33
+2V
LVPECL DUT 50
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Clock Timing Specifications
Cycle 1 SCLK SCLKX Tsc Tsh Tsl
The system clock timing is shown in Figure 13 and described in Table 37.
Figure 13 System Clock Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
CCLKn TccN Tcch Tccl
Table 37 System Clock Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tsc Tsh Tsl Tcc0 Tcc1 Tcc2 Tcc3 Tcch Tccl
*
System Cycle Time Sys Clk High Pulse Sys Clk Low Pulse CCLK0 Cycle Time CCLK1 Cycle Time CCLK2 Cycle Time CCLK3 Cycle Time CCLKm High Time CCLKm Low Time
3.76 45 45 6.43 6.43 6.43 6.43 40% 40% 60% 60% 55 55
ns
180MHz core clock Duty cycle* Duty cycle*
ns ns ns ns
% cycle pulse is high % cycle pulse is low
Pulse duty cycle measured at crossing voltage of SCLK/SCLKX The frequencies specified for CCLK0 - CCLK3 allow full flexibility for the C-3e NP. It is also possible to use one or more CCLKn inputs for other frequencies; contact your Motorola representative for more information.
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CP Timing Specifications
This section describes the timing for the following CP interfaces:
* * * * *
DS1/DS3 10/100 Ethernet Gigabit Ethernet OC-3 OC-12
DS1/DS3 Timing Specifications The DS1/DS3 interface timing is shown in Figure 14 and described in Table 38.
Figure 14 DS1/DS3 Ethernet Timing Diagram
Cycle 1 CPn_0 (TCLK) Tcdt CPn_2/3 (Tx) Tcdo Cycle 2 CPn_1 (RCLK) Tcdr CPn_4/5 (Rx) Tcds Tcdh Cycle 3 Cycle 4 Cycle 5 Cycle 2 Cycle 3 Cycle 4 Cycle 5
Table 38 DS1/DS3 Ethernet Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tcdt Tcdo Tcdr
DS1/DS3 Transmit Cycle Time DS1/DS3 Output Time DS1/DS3 Receive Cycle Time 3.0/3.0
647/22.4 400/15.0 647/22.4
ns ns ns
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Table 38 DS1/DS3 Ethernet Timing Description (continued)
SYMBOL PARAMETER MIN TYP MAX UNIT
Tcds Tcdh
DS1/DS3 Setup Time DS1/DS3 Hold Time
2.0 0
ns ns
10/100 Ethernet Timing Specifications The 10/100 Ethernet interface timing is shown in Figure 15 and described in Table 39.
Figure 15 10/100 Ethernet Timing Diagram
Cycle 1 CPn_0 (TCLK) Tcet CPn_2/3/6 (Tx) Tceo CPn_1/4/5 (Rx) Tces Tceh Cycle 2 Cycle 3 Cycle 4 Cycle 5
Table 39 10/100 Ethernet Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tcet Tceo Tces Tceh
*
Transmit Cycle Time* Output Time Setup Time Hold Time 3.0 2.0 0
20 15.0
ns ns ns ns
STD/Fast Ethernet
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Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in Table 40. The TBI interface timing is shown in Figure 16 and described in Table 41.
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
GMII / TBI Tx
CPn_0 (TCLK) Tcgt CPn_2-6 (Tx) CPn+1_2-6 (Tx) Tcgo Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
MII Tx
MII CPn_1 (TCLKI)
Cycle 1
Cycle 2
Cycle 3
Tcmt MII CPn_2-6 (Tx) Tcmo
TBI Rx
CPn+2_1 (RCLK) CPn+3_1 (RCLKN)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tctr Tctd CPn+2_2-6 (Rx) CPn+3_2-6 (Rx) Tcts Tcth
GMII/MII Rx
CPn+2_1 (RCLK)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tcgr CPn+2_2-6 (Rx) CPn+3_1-6 (Rx) Tcgs Tcgh
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Table 40 Gigabit GMII/MII Ethernet Interface Timing Description
SYMBOL GIGABIT PARAMETER MIN TYP MAX UNIT COMMENT
Tcgt Tcgo Tcgr Tcgs Tcgh Tcmt Tcmo
Transmit Cycle Time, GMII Output Time, GMII Receive Cycle Time Setup Time Hold Time Transmit Cycle Time, MII Output Time, MII 2 2.0 0.0 3.0
8.0 6.0 8.0
ns ns ns ns ns
40/400 12
ns ns
100BaseT/10BaseT
Table 41 Gigabit TBI Interface Timing Description
SYMBOL TBI PARAMETER MIN TYP MAX TOL UNIT
Tctt Tcto Tctr Tctd Tcts Tcth
*
Transmit Cycle Time Output Time Receive Cycle Time Rclk/Rclkn Deviation Setup Time Hold Time 2.0 0.0 3.0
8.0 6.0* 16.0 1.0
ns ns ns ns ns ns
For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns.
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OC-3 Timing Specifications The OC-3 interface timing is shown in Figure 17 and described in Table 42.
Figure 17 OC-3 Timing Diagram
Cycle 1 CPn_2 Tc3t CPn_3 Tc3i Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_0 CPn_1 Tc3r Tc3d CPn_4 Tc3s CPn_5 Tc3s Tc3h Tc3h
Table 42 OC-3 Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tc3t Tc3i Tc3r Tc3d Tc3s Tc3h
*
OC-3 Transmit Cycle Time OC-3 Pulse Width OC-3 Receive Cycle Time* OC-3 Clock Duty Cycle OC-3 Setup Time OC-3 Hold Time 2.0 6.0 40 2.0 0.0
6.43
ns ns ns 60 % ns ns
155.52MHz
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OC-12 Timing Specifications The OC-12 interface timing is shown in Figure 18 and described in Table 43.
Figure 18 OC-12 Timing Diagram
Cycle 1 CPn_1 (TCLKI) Tc12i Tc12d CPn_0 (TCLK) Tc12t CPn+1_2-5 (Tx) Tc12o Cycle 1 Cycle 2 Cycle 3 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_1 (RCLK) Tc12r CPn+2_2-6 (Rx) CPn+3_2-5 (Rx) Tc12s Tc12h
Table 43 OC-12 Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tc12i Tc12d Tc12t Tc12o Tc12r Tc12s Tc12h
*
OC-12 Transmit Cycle Time* OC-3 Clock Duty Cycle OC-12 Transmit Cycle Time OC-12 Output Time OC-12 Receive Cycle Time OC-12 Setup Time OC-12 Hold Time 3.0 12.0 2.0 0.0 40
12.86 60 12.86 10.0 12.86
ns % ns ns ns ns ns
Input from PHY Output from C-3e NP Aligned to TCLK
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Executive Processor Timing Specifications
The XP timing specifications include:
* * * *
PCI Timing Specifications MDIO Serial Interface Timing Specifications Low Speed Serial Interface Timing Specifications PROM Interface Timing Specifications
PCI Timing Specifications The PCI timing is shown in Figure 19 and described in Table 44.
Figure 19 PCI Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
PCLK Tpc PAD/P_ctl (output) Tpao PAD/P_ctl (input) Tpas PGNTX (input) Tpgs PIDSEL (input) Tpis Tpih Tpgh Tpah Tpaz Tpav
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Table 44 PCI Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tpc Tpas Tpah Tpao Tpaz Tpav Tpgs Tpgh Tpis Tpih
PCI Cycle Time* PAD/P_ctl Setup PAD/P_ctl Hold PAD/P_ctl Output PAD/P_ctl Clk to Tri PAD/P_ctl Clk to Driven PGNTX Setup PGNTX Hold PIDSEL Setup PIDSEL Hold PRSTX** PINTA**
15.0 3.0 0.0 2.0 2.0 2.0 5.1 0.0 3.0 0.0 6.0 6.0 6.0
ns ns ns ns ns ns ns ns ns ns ns ns
*
66MHz PCI P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX Not fully tested, values based on design/characterization. ** Asynchronous
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MDIO Serial Interface Timing Specifications The MDIO serial interface timing is shown in Figure 20 and described in Table 45.
Figure 20 MDIO Serial Interface Timing Diagram
Cycle 2 Cycle 3 Cycle 4
SICL Tsic SIDA (output) Tsods SIDA (input) Tsids Tsodh
Table 45 MDIO Serial Interface Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tsic Tsids Tsidh Tsods Tsodh
SICL Cycle Time SIDA Input Setup SIDA Input Hold SIDA Output Setup SIDA Output Hold
40 10 0.0 10 10
ns ns ns ns ns
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Low Speed Serial Interface Timing Specifications The low speed serial interface timing is shown in Figure 21 and described in Table 46.
Figure 21 Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
SICL Tslss SIDA Tslhs Tslhd Tslsd Tslc Tslst Tslb
Table 46 Low Speed Serial Interface Timing Description
SYMBOL PARAMETER MIN MAX UNIT
Tslc Tslss Tslhs Tslsd Tslhd Tslst Tslb Cmax
SICL Cycle Time Set-up Time for Repeated START Condition Hold Time START Condition Data Set-up Time Data Hold Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive load for each line of the bus
2500 600 600 250 0.0 600 1250 400
ns ns ns ns ns ns ns pF
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PROM Interface Timing Specifications The PROM interface timing is shown in Figure 22 and described in Table 47.
Figure 22 PROM Interface Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SPCK Tspc SPDI Tspis SPLD Tsplo SPDO Tspdo Tspih
Table 47 PROM Interface Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tspc Tspis Tspih Tsplo Tspdo
SPCK Cycle Time SPDI Setup SPDI Hold SPLD Output SPDO Output
40.0 10.0 0.0 Tsc Tsc Tsc + 3.0 Tsc + 3.0
ns ns ns ns ns
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Fabric Processor Timing Specifications
Cycle 1
The FP timing specifications are shown in Figure 23 and described in Table 48.
Figure 23 Fabric Processor Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
FRXCLK Tfrc FRXCTL (output) Tfrco FRXCTL (input) Tfrcs FINn Tfrds Tfrdh Tfrch Tfrcz Tfrcv
FTXCLK Tftc FTXCTL (output) Tftco FTXCTL (input) Tftcs FOUTn Tftdo Tftch Tftcz Tftcv
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Table 48 Fabric Processor Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tfrc Tfrcs Tfrch Tfrco Tfrcz Tfrcv Tfrds Tfrdh Tftc Tftcs Tftch Tftco Tftcz Tftcv Tftdo
*
FRX Cycle Time FRXCTL Setup FRXCTL Hold FRXCTL Output FRXCTL Clk to Tri* FRXCTL Clk to Driven* FIN Setup FIN Hold FTX Cycle Time FTXCTL Setup FTXCTL Hold FTXCTL Output FTXCTL Clk to Tri* FTXCTL Tri to Driven* FOUT Output
8.0 4.0 1.5 0.0 1.0 1.0 1.0 4.0 1.5 0.0 8.0 4.0 1.5 0.0 1.0 1.0 1.0 1.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Utopia2 Mode All other modes Utopia2 Mode All other modes Utopia2 Mode All other modes
Not fully tested, values based on design/characterization.
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BMU Timing Specifications
The BMU timing specifications are shown in Figure 24 and described in Table 49. The BMU synchronous DRAM interface is PC100-compliant and designed to work with industry standard SDRAM components with 12 or fewer address lines. The information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 24 BMU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
MDCLK Tmc M_ctl Tmco MAn Tmao MDn (output) Tmdo MDn (input) Tmds Tmdh Tmdz Tmdv
Table 49 BMU Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tmc Tmco Tmao Tmds Tmdh Tmdo Tmdz Tmdv
*
BMU Cycle Time BMU Ctrl Output BMU Addr Output BMU Data Setup BMU Data Hold BMU Data Output BMU Data Clk to Tri* BMU Data Clk to Driven*
8.0 0.8 0.8 0.5 1.1 0.8 0.8 0.8 4.5 4.5 4.5 3.9 3.9
ns ns ns ns ns ns ns ns
Not fully tested, values based on design/characterization.
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Table 50 Signal Groups in BMU Timing Diagrams
SIGNAL GROUP INCLUDED SIGNALS
Control (M_ctl) Address (MAn) Data (MDn)
MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM, MDQML MA0 - MA11 MD0 - MD129, MDECC0 - MDECC8
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TLU Timing Specifications
The TLU timing specifications are shown in Figure 25 and described in Table 51.
Figure 25 TLU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
TCLKI Ttc T_ctl Ttco TAn Ttao TDn (output) Ttdo TDn (input) Ttds Ttdh Ttdz Ttdv
Table 51 TLU Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Ttc Ttco Ttao Ttds Ttdh Ttdo Ttdz Ttdv
*
TLU Cycle Time TLU Ctrl Output TLU Addr Output TLU Data Setup TLU Data Hold TLU Data Output TLU Data Clk to Tri* TLU Data Clk to Driven*
8.0 0.8 0.8 1.0 1.2 0.8 0.8 0.8 4.2 4.2 4.2 3.9 3.9
ns ns ns ns ns ns ns ns
Not fully tested, values based on design/characterization.
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Table 52 Signal Groups in TLU Timing Diagrams
SIGNAL GROUP INCLUDED SIGNALS
Control (T_ctl) Address (TAn) Data (TDn)
TCE0X - TCE3X, TWE0X - TWE3X TA0 - TA21 TD0 - TD63, TPAR0-3
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QMU SRAM (Internal Mode) Timing Specifications
The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and described in Table 53.
Figure 26 QMU SRAM (Internal Mode) Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
QACLKI Tqc Q_ctl Tqco QAn Tqao QDn (output) Tqdo QDn (input) Tqds Tqdh Tqdz Tqdv
Table 53 QMU SRAM (Internal Mode) Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tqc Tqco Tqao Tqds Tqdh Tqdo
QMU Cycle Time QMU Ctrl Output QMU Addr Output QMU Data Setup QMU Data Hold QMU Data Output
6.7 0.8 0.8 0.8 0.8 0.9 4.4 4.4 4.4
ns ns ns ns ns ns Loading is 50 transmission line. Loading is 50 transmission line. Loading is 50 transmission line.
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Table 53 QMU SRAM (Internal Mode) Timing Description (continued)
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tqdz Tqdv
*
QMU Data Clk to Tri* 0.9 QMU Data Clk to Driven* 0.9
4.4 4.4
ns ns
Not fully tested, values based on design/characterization.
Table 54 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams
SIGNAL GROUP INCLUDED SIGNALS
Control (Q_ctl) Address (QAn) Data (QDn)
QWEX QA0-QA16 QD0-QD31, QDPL, QDPH
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QMU to Q-5/Q-3 (External Mode) Timing Specifications
The QMU to Q-5/Q-3 (External Mode) timing specifications are shown in Figure 27 and describded in Table 55.
Figure 27 QMU to Q-5/Q-3 (External Mode) Timing Diagram
Cycle 1 Tqec QACLKI Tqep QBCLKI Tqec Tqep Cycle 2
DQDATA
Tqeh Tqes Tqes
Tqeh
Tqec QACLKO Tqep QBCLKO Tqec Tqep
NQDATA
Tqeomax Tqeomax Tqeomin Tqeomin
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Table 55 QMU to Q-5/Q-3 (External Mode) Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tqec
QMU External Cycle Time
10.0
ns
QACLKO/QBCLKO derived from QACLKI/QBCLKI
Tqep Tqes Tqeh Tqeo
QMU CLKA-CLKB delta between rising edges QMU Input Data Setup QMU Input Data Hold QMU Data Output
4.8 0.6 0.8 -.85 1.3
ns ns ns ns Determines valid time for data from each clock rising edge
Table 56 Signal Groups in QMU to Q-5/Q-3 (External Mode) Timimg Diagrams
SIGNAL GROUP INCLUDED SIGNALS
Input Clocks (QnCLKI) Output Clocks (QnCLKO) Input Data (DQDATA) Output Data (NQDATA)
QACLKI, QBCLKI QACLKO, QBCLKO QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR QA0-16, QWEX, QD24-31
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Package Views
The C-3e network processor is an 728 pin (27 pins x 27 pins) Ball Grid Array (BGA) package as shown in the following illustrations. Table 57 defines the package measurements.
Figure 28 C-3e Network Processor BGA Package Side View
A4 A2 A3 A A1 Seating Plane
HiTCE: Green ceramic is thermally matched to FR4 circuit board.
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Figure 29 C-3e Network Processor BGA Package (Bottom View)
D D1 e
AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
1 2 3 45 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
e
E1
E
b
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MOTOROLA GENERAL BUSINESS INFORMATION
Package Views
105
Figure 30 C-3e Network Processor BGA (Top View)
Probe Pad Die
1.65
Optional Capacitor Pads
Optional Capacitor Pads
0.7
1.70
18ARS10518D001
MOTOROLA GENERAL BUSINESS INFORMATION
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CHAPTER 4: MECHANICAL SPECIFICATIONS
Package Measurements
Table 57 defines the C-3e NP package measurements, providing nominal, minimum, and maximum sizes where appropriate.
Table 57 Package Measurements (Reference Figure 28, Figure 29 and Figure 30 for Symbols)
SYMBOL DEFINITION NOM. (MM) MIN. (MM) MAX. (MM)
A A1 A2 A3 A4 D D1 E E1 e b
Overall Ball height C4 and Die Body thickness Capacitor pad Body size Ball footprint (X) Body size Ball footprint (Y) Ball pitch Ball diameter
3.11 0.70 0.86 1.55 29.00 26.00 29.00 26.00 1.00 0.70
2.83 0.6 1.41 28.80 28.80
3.39 0.8 1.69 0.6 29.20 29.20
At Motorola's discretion up to fourteen (14) capacitors may or may not be attached on the top of the package.
Marking Codes
Table 58 explains the marking on the C-3e NP.
Table 58 C-3e Network Processor Marking Codes
MARKING (EXPLANATION OF CODES)
Top Bottom Pin 1 Marking
Logo/Part#/Date Code N/A Chamfered Corner
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Reflow
107
Reflow
Typical Reflow Profile for the C-3e Switch Module comprises: 1 Follow the guidelines recommended by your solder paste supplier. Flux requirements must be met for best solderability. 2 The temperature profile should be carefully characterized to ensure uniform temperature across the board and package. Solder ball voiding may be affected by ramp rates and dwell times below and above liquids. 3 A nitrogen atmosphere is not required, but will make the process more robust. It can make a difference for marginally solderable PC board pads. 4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can be used.
MOTOROLA GENERAL BUSINESS INFORMATION
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CHAPTER 4: MECHANICAL SPECIFICATIONS
C3ENPA1-DS/D REV 03
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C3ENPA1-DS/D Rev 03
INDEX
Symbols
10/100 Ethernet (RMII) Configuration 35 10/100 Ethernet Signals 35 10/100 Ethernet Timing Description 82 10/100 Ethernet Timing Diagram 82 10/100 Ethernet Timing Specifications 82
A
Absolute Maximum Ratings 71 AC Timing Specifications 79
B
Block Diagram, C-3e Network Processor 20 BMU SDRAM Interface Signals 51 BMU Signal Groups 95 BMU Timing Description 94 BMU Timing Diagram 94 BMU Timing Specifications 94 Boundary Scan Cell Types 67 Boundary Scan Description Language 70 Bringup Clock Timing Diagram 74 Buffer Management Unit 24
Channel Processors 22 Channel Processors Physical Interface Signals and Pins Grouped by Clusters 33 Clock and Reference Signals 31 Clock Signals 31 Clock Timing Specifications 80 Configuration 10/100 Ethernet (RMII) 35 DS1/T1 Framer Interface 34 FibreChannel TBI 38 Gigabit Ethernet 38 Gigabit Ethernet (GMII) 36 SONET OC-12 Transceiver Interface 41 SONET OC-3 Transceiver Interface 40 Configurations GMII/TBI Transmit and Receive Pin 36 CP Timing Specifications 81
D
Data Registers JTAG 67 DC Characteristics 73 Description Functional 19 Description Language Boundary Scan 70 Descriptions Signal 27 Diagram 10/100 Ethernet Timing 82 BMU Timing 94 Bringup Clock Timing 74 DS1/DS3 Ethernet Timing 81 Fabric Processor Timing 92 Gigabit Ethernet (TBI) Timing 83 C3ENPA1-DS/D REV 03
C
C-3e Network Processor Absolute Maximum Ratings 71 C-3e Network Processor BGA Package, Bottom View 104 C-3e Network Processor BGA Package, Side View 103 C-3e Network Processor Capacitance Data 73 C-3e Network Processor DC Characteristics 73 C3e Network Processor Power and Thermal Characteristics 75 C-3e NP Channel Processors 22 Channel Processor Interface Signals 31 MOTOROLA GENERAL BUSINESS INFORMATION
110
INDEX
Low Speed Serial Interface Timing 90 MDIO Serial Interface Timing 89 OC-3 Timing 85 PCI Timing 87 Pinout 28 PROM Interface 46 PROM Interface Timing 91 QMU Timing 98 Signal Groups in BMU Timing 95 Signal Groups in QMU Timing 99 Signal Groups in TLU Timing 97 System Clock Timing 80 TLU Timing 96 Diagram, Block C-3e Network Processor 20 DS1/DS3 Ethernet Timing Description 81 DS1/DS3 Ethernet Timing Diagram 81 DS1/DS3 Timing Specifications 81 DS1/T1 Framer Interface Configuration 34 DS1/T1 Framer Interface Signals 34
G
General System Interface Signal 48 Gigabit Ethernet (GMII) Configuration 36 Gigabit Ethernet (GMII) Signals One Cluster Example 37 Gigabit Ethernet (TBI) Timing Description 84, 84 Gigabit Ethernet (TBI) Timing Diagram 83 Gigabit Ethernet and FibreChannel TBI Configuration 38 Gigabit Ethernet and FibreChannel TBI Signals Example 38 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 83 GMII/TBI Transmit and Receive Pin Configurations 36
I
IDcode Register 69 Instruction Register Instructions 69
J E
Electrical Specifications 71 Absolute Maximum Ratings 71 Executive Processor 23 PCI 23 PROM Interface 24 Serial Bus Interface 23 System Interface Signals 43 System Interfaces 23 Executive Processor Timing Specifications 87 JTAG Data Registers 67 JTAG Identification Code and Its Sub-components 69 JTAG Instruction Register 69 JTAG Internal Register Descriptions 67 JTAG Support Pinouts 67
L
Low Speed Serial Interface Timing Description 90 Low Speed Serial Interface Timing Diagram 90 Low Speed Serial Interface Timing Specifications 90 LVPECL Specifications 30 LVTTL Specifications 30
F
Fabric Interface Pin Mapping Utopia2/Utopia3 ATM Mode 50 Utopia2/Utopia3 PHY Mode 50 Fabric Processor 24 Fabric Processor Interface Signals 49 Fabric Processor Timing Description 93 Fabric Processor Timing Diagram 92 Fabric Processor Timing Specifications 92 Functional Description 19
M
MDIO Serial Interface Timing Description 89 MDIO Serial Interface Timing Diagram 89 MDIO Serial Interface Timing Specifications 89 Measurements C-3e Network Processor 106 Mechanical Specifications 103
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MOTOROLA GENERAL BUSINESS INFORMATION
INDEX
111
Miscellaneous Test Signals for JTAG, Scan, and Internal Test Routines 57
Queue Management Unit 26
O
OC-12 Signals 41 OC-12 Timing Description 86 OC-12 Timing Specifications 86 OC-3 Signals 40 OC-3 Timing Description 85 OC-3 Timing Diagram 85 OC-3 Timing Specifications 85 Operating Conditions, Recommended 72
R
Recommended Operating Conditions 72 Register IDcode 69 JTAG Instruction 69
S
Serial Interface Signals 44 Serial Port Signals 44 Signal General System Interface 48 Signal Descriptions 27 Signal Summary 27 Signals 10/100 Ethernet 35 BMU SDRAM Interface 51 Channel Processor Interface 31 Clock 31 Clock and Reference 31 DS1/T1 Framer Interface 34 Fabric Processor Interface 49 Grouped by Pin Number 58 OC-12 41 OC-3 40 PCI 43 Power Supply 56 PROM Interface 45 QMU SRAM Interface 54, 55 Serial Interface 44 Serial Port 44 Test 57 TLU SRAM Interface 53 SONET OC-12 Transceiver Interface Configuration 41 SONET OC-3 Transceiver Interface Configuration 40 Specifications 10/100 Ethernet Timing 82 AC Timing 79 BMU Timing 94 Clock Timing 80 CP Timing 81 DS1/DS3 Timing 81 C3ENPA1-DS/D REV 03
P
Package Measurements 106 PCI Signals 43 PCI Timing Description 88 PCI Timing Diagram 87 PCI Timing Specifications 87 Pin Descriptions Grouped by Function 30 Pin Locations 28 Pin Number Signals Groups 58 Pinout Diagram 28 Power Sequencing 74, 75 Power Supply Signals 56 Processor, Executive 23 Processor, Fabric 24 PROM Interface Diagram 46 PROM Interface Signals 45 PROM Interface Timing Description 91 PROM Interface Timing Diagram 91 PROM Interface Timing Outline 47 PROM Interface Timing Specifications 91
Q
QMU Signal Groups 99 QMU SRAM (Internal Mode) Timing Diagram 98 QMU SRAM Interface Signals 54, 55 QMU Timing Description 98 QMU Timing Specifications 98 QMU to Q-5/Q-3 (External Mode) Timing Diagram 100 MOTOROLA GENERAL BUSINESS INFORMATION
112
INDEX
Electrical 71 Executive Processor Timing 87 Fabric Processor Timing 92 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 83 Low Speed Serial Interface Timing 90 MDIO Serial Interface Timing 89 Mechanical 103 OC-12 Timing 86 OC-3 Timing 85 PCI Timing 87 PROM Interface Timing 91 QMU Timing 98 TLU Timing 96 XP Timing 87 System Clock Timing Description 80 System Clock Timing Diagram 80 System Interfaces Executive Processor 23
Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test Routines 57 Timing Outline PROM Interface 47 TLU Signal Groups 97 TLU SRAM Interface Signals 53 TLU Timing Description 96 TLU Timing Diagram 96 TLU Timing Specifications 96 Transceiver Interface Configuration SONET OC-12 41 SONET OC-3 40 Transmit and Receive Pin Combinations for Gigabit Ethernet and FibreChannel 36
U
Utopia2/Utopia3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping 50 Utopia2/Utopia3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping 50
T
Table Lookup Unit 25 Test Signals 57
X
XP Timing Specifications 87
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
Motorola, Inc. C-Port Family of Network Processors 120 Water Street, No. Andover, MA 01845 Voice: (978) 773-2300 FAX: (978) 773-2301

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